1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #ifndef _ASM_ARCH_SCU_AST2600_H 7 #define _ASM_ARCH_SCU_AST2600_H 8 9 /* 10 * register offset 11 */ 12 #define AST_SCU_CONFIG 0x004 13 #define AST_SCU_MPLL_PARAM 0x200 14 #define AST_SCU_MPLL_EXT_PARAM 0x204 15 #define AST_SCU_FPGA_PLL 0x400 16 #define AST_SCU_HW_STRAP 0x500 17 18 /* 19 * bit-field 20 */ 21 #define SCU_UNLOCK_VALUE 0x1688a8a8 22 23 #define SCU_HWSTRAP_VGAMEM_SHIFT 2 24 #define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT) 25 #define SCU_HWSTRAP_MAC1_RGMII (1 << 6) 26 #define SCU_HWSTRAP_MAC2_RGMII (1 << 7) 27 #define SCU_HWSTRAP_DDR4 (1 << 24) 28 #define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23) 29 30 #define SCU_HWSTRAP_VGAMEM_SHIFT 13 31 #define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT) 32 33 #define SCU_HWSTRAP_DDR3 (1 << 25) 34 35 #define SCU_MPLL_DENUM_SHIFT 0 36 #define SCU_MPLL_DENUM_MASK 0x1f 37 #define SCU_MPLL_NUM_SHIFT 5 38 #define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT) 39 #define SCU_MPLL_POST_SHIFT 13 40 #define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT) 41 #define SCU_PCLK_DIV_SHIFT 23 42 #define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT) 43 #define SCU_HPLL_DENUM_SHIFT 0 44 #define SCU_HPLL_DENUM_MASK 0x1f 45 #define SCU_HPLL_NUM_SHIFT 5 46 #define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT) 47 #define SCU_HPLL_POST_SHIFT 13 48 #define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT) 49 50 #define SCU_MACCLK_SHIFT 16 51 #define SCU_MACCLK_MASK (7 << SCU_MACCLK_SHIFT) 52 53 #define SCU_MISC2_RGMII_HPLL (1 << 23) 54 #define SCU_MISC2_RGMII_CLKDIV_SHIFT 20 55 #define SCU_MISC2_RGMII_CLKDIV_MASK (3 << SCU_MISC2_RGMII_CLKDIV_SHIFT) 56 #define SCU_MISC2_RMII_MPLL (1 << 19) 57 #define SCU_MISC2_RMII_CLKDIV_SHIFT 16 58 #define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT) 59 #define SCU_MISC2_UARTCLK_SHIFT 24 60 61 #define SCU_MISC_D2PLL_OFF (1 << 4) 62 #define SCU_MISC_UARTCLK_DIV13 (1 << 12) 63 #define SCU_MISC_GCRT_USB20CLK (1 << 21) 64 65 #define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT 0 66 #define SCU_MICDS_MAC1RGMII_TXDLY_MASK (0x3f\ 67 << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT) 68 #define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT 6 69 #define SCU_MICDS_MAC2RGMII_TXDLY_MASK (0x3f\ 70 << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT) 71 #define SCU_MICDS_MAC1RMII_RDLY_SHIFT 12 72 #define SCU_MICDS_MAC1RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT) 73 #define SCU_MICDS_MAC2RMII_RDLY_SHIFT 18 74 #define SCU_MICDS_MAC2RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT) 75 #define SCU_MICDS_MAC1RMII_TXFALL (1 << 24) 76 #define SCU_MICDS_MAC2RMII_TXFALL (1 << 25) 77 #define SCU_MICDS_RMII1_RCLKEN (1 << 29) 78 #define SCU_MICDS_RMII2_RCLKEN (1 << 30) 79 #define SCU_MICDS_RGMIIPLL (1 << 31) 80 81 82 /* Bits 16-27 in the register control pin functions for I2C devices 3-14 */ 83 #define SCU_PINMUX_CTRL5_I2C (1 << 16) 84 85 /* 86 * The values are grouped by function, not by register. 87 * They are actually scattered across multiple loosely related registers. 88 */ 89 #define SCU_PIN_FUN_MAC1_MDC (1 << 30) 90 #define SCU_PIN_FUN_MAC1_MDIO (1 << 31) 91 #define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0) 92 #define SCU_PIN_FUN_MAC2_MDIO (1 << 2) 93 #define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1) 94 #define SCU_PIN_FUN_SCL1 (1 << 12) 95 #define SCU_PIN_FUN_SCL2 (1 << 14) 96 #define SCU_PIN_FUN_SDA1 (1 << 13) 97 #define SCU_PIN_FUN_SDA2 (1 << 15) 98 99 #define SCU_CLKSTOP_MAC1 (1 << 20) 100 #define SCU_CLKSTOP_MAC2 (1 << 21) 101 102 #define SCU_D2PLL_EXT1_OFF (1 << 0) 103 #define SCU_D2PLL_EXT1_BYPASS (1 << 1) 104 #define SCU_D2PLL_EXT1_RESET (1 << 2) 105 #define SCU_D2PLL_EXT1_MODE_SHIFT 3 106 #define SCU_D2PLL_EXT1_MODE_MASK (3 << SCU_D2PLL_EXT1_MODE_SHIFT) 107 #define SCU_D2PLL_EXT1_PARAM_SHIFT 5 108 #define SCU_D2PLL_EXT1_PARAM_MASK (0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT) 109 110 #define SCU_D2PLL_NUM_SHIFT 0 111 #define SCU_D2PLL_NUM_MASK (0xff << SCU_D2PLL_NUM_SHIFT) 112 #define SCU_D2PLL_DENUM_SHIFT 8 113 #define SCU_D2PLL_DENUM_MASK (0x1f << SCU_D2PLL_DENUM_SHIFT) 114 #define SCU_D2PLL_POST_SHIFT 13 115 #define SCU_D2PLL_POST_MASK (0x3f << SCU_D2PLL_POST_SHIFT) 116 #define SCU_D2PLL_ODIV_SHIFT 19 117 #define SCU_D2PLL_ODIV_MASK (7 << SCU_D2PLL_ODIV_SHIFT) 118 #define SCU_D2PLL_SIC_SHIFT 22 119 #define SCU_D2PLL_SIC_MASK (0x1f << SCU_D2PLL_SIC_SHIFT) 120 #define SCU_D2PLL_SIP_SHIFT 27 121 #define SCU_D2PLL_SIP_MASK (0x1f << SCU_D2PLL_SIP_SHIFT) 122 123 #define SCU_CLKDUTY_DCLK_SHIFT 0 124 #define SCU_CLKDUTY_DCLK_MASK (0x3f << SCU_CLKDUTY_DCLK_SHIFT) 125 #define SCU_CLKDUTY_RGMII1TXCK_SHIFT 8 126 #define SCU_CLKDUTY_RGMII1TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII1TXCK_SHIFT) 127 #define SCU_CLKDUTY_RGMII2TXCK_SHIFT 16 128 #define SCU_CLKDUTY_RGMII2TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII2TXCK_SHIFT) 129 130 #ifndef __ASSEMBLY__ 131 132 struct ast2600_clk_priv { 133 struct ast2600_scu *scu; 134 }; 135 136 struct hw_strap { 137 u32 hwstrap; /* 0x508 */ 138 u32 hwstrap_clr; /* 0x504 */ 139 u32 hwstrap_protect; /* 0x508 */ 140 }; 141 142 struct ast2600_scu { 143 u32 protection_key; /* 0x000 */ 144 u32 chip_id0; /* 0x004 */ 145 u32 reserve_0x08; /* 0x008 */ 146 u32 reserve_0x0C; /* 0x00C */ 147 u32 reserve_0x10; /* 0x010 */ 148 u32 chip_id1; /* 0x014 */ 149 u32 reserve_0x18; /* 0x018 */ 150 u32 reserve_0x1C; /* 0x01C */ 151 u32 reserve_0x20; /* 0x020 */ 152 u32 reserve_0x24; /* 0x024 */ 153 u32 reserve_0x28; /* 0x028 */ 154 u32 reserve_0x2c; /* 0x02C */ 155 u32 reserve_0x30; /* 0x030 */ 156 u32 reserve_0x34; /* 0x034 */ 157 u32 reserve_0x38; /* 0x038 */ 158 u32 reserve_0x3C; /* 0x03C */ 159 u32 sysreset_ctrl1; /* 0x040 */ 160 u32 sysreset_clr_ctrl1; /* 0x044 */ 161 u32 reserve_0x48; /* 0x048 */ 162 u32 reserve_0x4C; /* 0x04C */ 163 u32 sysreset_ctrl2; /* 0x050 */ 164 u32 sysreset_clr_ctrl2; /* 0x054 */ 165 u32 reserve_0x58; /* 0x058 */ 166 u32 reserve_0x5C; /* 0x05C */ 167 u32 extrst_sel1; /* 0x060 */ 168 u32 sysrst_evet_log1_1; /* 0x064 */ 169 u32 sysrst_evet_log1_2; /* 0x068 */ 170 u32 reserve_0x6C; /* 0x06C */ 171 u32 extrst_sel2; /* 0x070 */ 172 u32 sysrst_evet_log2_1; /* 0x074 */ 173 u32 sysrst_evet_log2_2; /* 0x078 */ 174 u32 reserve_0x7C; /* 0x07C */ 175 u32 clk_stop_ctrl1; /* 0x080 */ 176 u32 reserve_0x84; /* 0x084 */ 177 u32 reserve_0x88; /* 0x088 */ 178 u32 reserve_0x8C; /* 0x08C */ 179 u32 clk_stop_ctrl2; /* 0x090 */ 180 u32 reserve_0x94; /* 0x094 */ 181 u32 reserve_0x98; /* 0x098 */ 182 u32 reserve_0x9C; /* 0x09C */ 183 u32 reserve_0xA0; /* 0x0A0 */ 184 u32 reserve_0xA4; /* 0x0A4 */ 185 u32 reserve_0xA8; /* 0x0A8 */ 186 u32 reserve_0xAC; /* 0x0AC */ 187 u32 reserve_0xB0; /* 0x0B0 */ 188 u32 reserve_0xB4; /* 0x0B4 */ 189 u32 reserve_0xB8; /* 0x0B8 */ 190 u32 reserve_0xBC; /* 0x0BC */ 191 u32 misc_ctrl1; /* 0x0C0 */ 192 u32 misc_ctrl2; /* 0x0C4 */ 193 u32 backdoor_ctrl; /* 0x0C8 */ 194 u32 reserve_0xCC; /* 0x0CC */ 195 u32 misc_ctrl3; /* 0x0D0 */ 196 u32 misc_ctrl4; /* 0x0D4 */ 197 u32 reserve_0xD8; /* 0x0D8 */ 198 u32 reserve_0xDC; /* 0x0DC */ 199 u32 reserve_0xE0; /* 0x0E0 */ 200 u32 reserve_0xE4; /* 0x0E4 */ 201 u32 reserve_0xE8; /* 0x0E8 */ 202 u32 reserve_0xEC; /* 0x0EC */ 203 u32 reserve_0xF0; /* 0x0F0 */ 204 u32 reserve_0xF4; /* 0x0F4 */ 205 u32 reserve_0xF8; /* 0x0F8 */ 206 u32 reserve_0xFC; /* 0x0FC */ 207 u32 soc_scratch[4]; /* 0x100 */ 208 u32 reserve_0x110; /* 0x110 */ 209 u32 reserve_0x114; /* 0x114 */ 210 u32 reserve_0x118; /* 0x118 */ 211 u32 reserve_0x11C; /* 0x11C */ 212 u32 cpu_scratch_wp; /* 0x120 */ 213 u32 reserve_0x124[23]; /* 0x124 */ 214 u32 cpu_scratch[32]; /* 0x180 */ 215 u32 h_pll_param; /* 0x200 */ 216 u32 h_pll_ext_param; /* 0x204 */ 217 u32 reserve_0x208; /* 0x208 */ 218 u32 reserve_0x20C; /* 0x20C */ 219 u32 a_pll_param; /* 0x210 */ 220 u32 a_pll_ext_param; /* 0x214 */ 221 u32 reserve_0x218; /* 0x218 */ 222 u32 reserve_0x21C; /* 0x21C */ 223 u32 m_pll_param; /* 0x220 */ 224 u32 m_pll_ext_param; /* 0x224 */ 225 u32 reserve_0x228; /* 0x228 */ 226 u32 reserve_0x22C; /* 0x22C */ 227 u32 reserve_0x230[4]; /* 0x230 */ 228 u32 e_pll_param; /* 0x240 */ 229 u32 e_pll_ext_param; /* 0x244 */ 230 u32 reserve_0x248; /* 0x248 */ 231 u32 reserve_0x24C; /* 0x24C */ 232 u32 reserve_0x250[4]; /* 0x250 */ 233 u32 d_pll_param; /* 0x260 */ 234 u32 d_pll_ext_param; /* 0x264 */ 235 u32 reserve_0x268; /* 0x268 */ 236 u32 reserve_0x26C; /* 0x26C */ 237 u32 reserve_0x270[36]; /* 0x270 */ 238 u32 clk_sel1; /* 0x300 */ 239 u32 clk_sel2; /* 0x304 */ 240 u32 reserve_0x308; /* 0x308 */ 241 u32 reserve_0x30C; /* 0x30C */ 242 u32 clk_sel3; /* 0x310 */ 243 u32 clk_sel4; /* 0x314 */ 244 u32 reserve_0x318; /* 0x318 */ 245 u32 reserve_0x31C; /* 0x31C */ 246 u32 freq_counter_ctrl1; /* 0x320 */ 247 u32 freq_counter_cmp1; /* 0x324 */ 248 u32 reserve_0x328; /* 0x328 */ 249 u32 uart_24m_ref_hpll; /* 0x32C */ 250 u32 freq_counter_ctrl2; /* 0x330 */ 251 u32 freq_counter_cmp2; /* 0x334 */ 252 u32 uart_24m_ref_uxclk; /* 0x338 */ 253 u32 uart_24m_ref_apll; /* 0x33C */ 254 u32 mac12_clk_delay; /* 0x340 */ 255 u32 reserve_0x344; /* 0x344 */ 256 u32 mac12_clk_delay_100M;/* 0x348 */ 257 u32 mac12_clk_delay_10M;/* 0x34c */ 258 u32 mac34_clk_delay; /* 0x350 */ 259 u32 reserve_0x354; /* 0x354 */ 260 u32 mac34_clk_delay_100M;/* 0x358 */ 261 u32 mac34_clk_delay_10M;/* 0x35c */ 262 u32 clk_duty_meas_ctrl; /* 0x360 */ 263 u32 clk_duty_sel0; /* 0x364 */ 264 u32 clk_duty_sel1; /* 0x368 */ 265 u32 clk_duty_meas_res; /* 0x36C */ 266 u32 clk_duty_meas_ctr2; /* 0x370 */ 267 u32 clk_duty_sel2; /* 0x374 */ 268 u32 reserve_0x378[34]; /* 0x378 */ 269 u32 pinmux_ctrl1[64]; /* 0x400 ~ 0x500 */ 270 struct hw_strap hwstrap1; /* 0x500 */ 271 u32 reserve_0x50C; /* 0x50C */ 272 struct hw_strap hwstrap2; /* 0x510 */ 273 u32 reserve_0x51C; /* 0x51C */ 274 u32 rng_ctrl; /* 0x520 */ 275 u32 rng_data; /* 0x524 */ 276 u32 reserve_0x528[6]; /* 0x528 */ 277 u32 pwr_save_wakeup_en1;/* 0x540 */ 278 u32 pwr_save_wakeup_ctrl1;/* 0x544 */ 279 u32 reserve_0x548[2]; /* 0x548 */ 280 u32 pwr_save_wakeup_en2;/* 0x550 */ 281 u32 pwr_save_wakeup_ctrl2;/* 0x554 */ 282 u32 reserve_0x558[2]; /* 0x558 */ 283 u32 intr1_ctrl_sts; /* 0x560 */ 284 u32 reserve_0x564[3]; /* 0x564 */ 285 u32 intr2_ctrl_sts; /* 0x570 */ 286 u32 reserve_0x574[3]; /* 0x574 */ 287 u32 reserve_0x580[4]; /* 0x580 */ 288 u32 opt_ctrl; /* 0x590 */ 289 u32 hw_config; /* 0x594 */ 290 u32 reserve_0x598[6]; /* 0x598 */ 291 u32 chip_unique_id[8]; /* 0x5B0 */ 292 u32 reserve_0x5E0[8]; /* 0x5E0 */ 293 u32 disgpio_in_pull_down0; /* 0x610 */ 294 u32 disgpio_in_pull_down1; /* 0x614 */ 295 u32 disgpio_in_pull_down2; /* 0x618 */ 296 u32 disgpio_in_pull_down3; /* 0x61C */ 297 u32 reserve_0x620[4]; /* 0x620 */ 298 u32 disgpio_in_pull_down4; /* 0x630 */ 299 u32 disgpio_in_pull_down5; /* 0x634 */ 300 u32 disgpio_in_pull_down6; /* 0x638 */ 301 u32 reserve_0x63C[5]; /* 0x63Cs */ 302 u32 sli_driving_strength; /* 0x650 */ 303 u32 reserve_0x654[235]; /* 0x654 */ 304 u32 cm3_ctrl; /* 0xA00 */ 305 u32 cm3_base; /* 0xA04 */ 306 u32 cm3_instr_mem_addr; /* 0xA08 */ 307 u32 cm3_data_mem_addr; /* 0xA0C */ 308 u32 reserve_0xA10[12]; /* 0xA10 */ 309 u32 cm3_cache_area; /* 0xA40 */ 310 u32 cm3_cache_invalid_ctrl; /* 0xA44 */ 311 u32 cm3_cache_fun_ctrl; /* 0xA48 */ 312 u32 reserve_0xA4C[108]; /* 0xA4C */ 313 u32 pci_config[3]; /* 0xC00 */ 314 u32 reserve_0xC0C[5]; /* 0xC0C */ 315 u32 pcie_config; /* 0xC20 */ 316 u32 mmio_decode; /* 0xC24 */ 317 u32 reloc_ctrl_decode[2]; /* 0xC28 */ 318 u32 reserve_0xC30[4]; /* 0xC30 */ 319 u32 mailbox_addr; /* 0xC40 */ 320 u32 shared_sram_decode[2]; /* 0xC44 */ 321 u32 bmc_rev_id; /* 0xC4C */ 322 u32 reserve_0xC50[5]; /* 0xC50 */ 323 u32 bmc_device_id; /* 0xC64 */ 324 u32 reserve_0xC68[102]; /* 0xC68 */ 325 u32 vga_scratch[8]; /* 0xE00 */ 326 }; 327 328 /** 329 * ast_get_clk() - get a pointer to Clock Driver 330 * 331 * @devp, OUT - pointer to Clock Driver 332 * @return zero on success, error code (< 0) otherwise. 333 */ 334 int ast_get_clk(struct udevice **devp); 335 336 /** 337 * ast_get_scu() - get a pointer to SCU registers 338 * 339 * @return pointer to struct ast2600_scu on success, ERR_PTR otherwise 340 */ 341 void *ast_get_scu(void); 342 343 #endif /* __ASSEMBLY__ */ 344 345 #endif /* _ASM_ARCH_SCU_AST2600_H */ 346