1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2016 Google, Inc 4 */ 5 #ifndef _ASM_ARCH_SCU_AST2500_H 6 #define _ASM_ARCH_SCU_AST2500_H 7 8 #define SCU_UNLOCK_VALUE 0x1688a8a8 9 10 #define SCU_HWSTRAP_VGAMEM_SHIFT 2 11 #define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT) 12 #define SCU_HWSTRAP_MAC1_RGMII (1 << 6) 13 #define SCU_HWSTRAP_MAC2_RGMII (1 << 7) 14 #define SCU_HWSTRAP_AXIAHB_DIV_SHIFT 9 15 #define SCU_HWSTRAP_AXIAHB_DIV_MASK (7 << SCU_HWSTRAP_AXIAHB_DIV_SHIFT) 16 #define SCU_HWSTRAP_DDR4 (1 << 24) 17 #define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23) 18 19 #define SCU_MPLL_DENUM_SHIFT 0 20 #define SCU_MPLL_DENUM_MASK 0x1f 21 #define SCU_MPLL_NUM_SHIFT 5 22 #define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT) 23 #define SCU_MPLL_POST_SHIFT 13 24 #define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT) 25 #define SCU_PCLK_DIV_SHIFT 23 26 #define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT) 27 #define SCU_HPLL_DENUM_SHIFT 0 28 #define SCU_HPLL_DENUM_MASK 0x1f 29 #define SCU_HPLL_NUM_SHIFT 5 30 #define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT) 31 #define SCU_HPLL_POST_SHIFT 13 32 #define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT) 33 34 #define SCU_MACCLK_SHIFT 16 35 #define SCU_MACCLK_MASK (7 << SCU_MACCLK_SHIFT) 36 37 #define SCU_MISC2_RGMII_HPLL (1 << 23) 38 #define SCU_MISC2_RGMII_CLKDIV_SHIFT 20 39 #define SCU_MISC2_RGMII_CLKDIV_MASK (3 << SCU_MISC2_RGMII_CLKDIV_SHIFT) 40 #define SCU_MISC2_RMII_MPLL (1 << 19) 41 #define SCU_MISC2_RMII_CLKDIV_SHIFT 16 42 #define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT) 43 #define SCU_MISC2_UARTCLK_SHIFT 24 44 45 #define SCU_MISC_D2PLL_OFF (1 << 4) 46 #define SCU_MISC_UARTCLK_DIV13 (1 << 12) 47 #define SCU_MISC_GCRT_USB20CLK (1 << 21) 48 49 #define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT 0 50 #define SCU_MICDS_MAC1RGMII_TXDLY_MASK (0x3f\ 51 << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT) 52 #define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT 6 53 #define SCU_MICDS_MAC2RGMII_TXDLY_MASK (0x3f\ 54 << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT) 55 #define SCU_MICDS_MAC1RMII_RDLY_SHIFT 12 56 #define SCU_MICDS_MAC1RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT) 57 #define SCU_MICDS_MAC2RMII_RDLY_SHIFT 18 58 #define SCU_MICDS_MAC2RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT) 59 #define SCU_MICDS_MAC1RMII_TXFALL (1 << 24) 60 #define SCU_MICDS_MAC2RMII_TXFALL (1 << 25) 61 #define SCU_MICDS_RMII1_RCLKEN (1 << 29) 62 #define SCU_MICDS_RMII2_RCLKEN (1 << 30) 63 #define SCU_MICDS_RGMIIPLL (1 << 31) 64 65 66 67 /* Bits 16-27 in the register control pin functions for I2C devices 3-14 */ 68 #define SCU_PINMUX_CTRL5_I2C (1 << 16) 69 70 /* 71 * The values are grouped by function, not by register. 72 * They are actually scattered across multiple loosely related registers. 73 */ 74 #define SCU_PIN_FUN_MAC1_MDC (1 << 30) 75 #define SCU_PIN_FUN_MAC1_MDIO (1 << 31) 76 #define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0) 77 #define SCU_PIN_FUN_MAC2_MDIO (1 << 2) 78 #define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1) 79 #define SCU_PIN_FUN_SCL1 (1 << 12) 80 #define SCU_PIN_FUN_SCL2 (1 << 14) 81 #define SCU_PIN_FUN_SDA1 (1 << 13) 82 #define SCU_PIN_FUN_SDA2 (1 << 15) 83 84 #define SCU_D2PLL_EXT1_OFF (1 << 0) 85 #define SCU_D2PLL_EXT1_BYPASS (1 << 1) 86 #define SCU_D2PLL_EXT1_RESET (1 << 2) 87 #define SCU_D2PLL_EXT1_MODE_SHIFT 3 88 #define SCU_D2PLL_EXT1_MODE_MASK (3 << SCU_D2PLL_EXT1_MODE_SHIFT) 89 #define SCU_D2PLL_EXT1_PARAM_SHIFT 5 90 #define SCU_D2PLL_EXT1_PARAM_MASK (0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT) 91 92 #define SCU_D2PLL_NUM_SHIFT 0 93 #define SCU_D2PLL_NUM_MASK (0xff << SCU_D2PLL_NUM_SHIFT) 94 #define SCU_D2PLL_DENUM_SHIFT 8 95 #define SCU_D2PLL_DENUM_MASK (0x1f << SCU_D2PLL_DENUM_SHIFT) 96 #define SCU_D2PLL_POST_SHIFT 13 97 #define SCU_D2PLL_POST_MASK (0x3f << SCU_D2PLL_POST_SHIFT) 98 #define SCU_D2PLL_ODIV_SHIFT 19 99 #define SCU_D2PLL_ODIV_MASK (7 << SCU_D2PLL_ODIV_SHIFT) 100 #define SCU_D2PLL_SIC_SHIFT 22 101 #define SCU_D2PLL_SIC_MASK (0x1f << SCU_D2PLL_SIC_SHIFT) 102 #define SCU_D2PLL_SIP_SHIFT 27 103 #define SCU_D2PLL_SIP_MASK (0x1f << SCU_D2PLL_SIP_SHIFT) 104 105 #define SCU_CLKDUTY_DCLK_SHIFT 0 106 #define SCU_CLKDUTY_DCLK_MASK (0x3f << SCU_CLKDUTY_DCLK_SHIFT) 107 #define SCU_CLKDUTY_RGMII1TXCK_SHIFT 8 108 #define SCU_CLKDUTY_RGMII1TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII1TXCK_SHIFT) 109 #define SCU_CLKDUTY_RGMII2TXCK_SHIFT 16 110 #define SCU_CLKDUTY_RGMII2TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII2TXCK_SHIFT) 111 112 struct ast2500_clk_priv { 113 struct ast2500_scu *scu; 114 }; 115 116 struct ast2500_scu { 117 u32 protection_key; 118 u32 sysreset_ctrl1; 119 u32 clk_sel1; 120 u32 clk_stop_ctrl1; 121 u32 freq_counter_ctrl; 122 u32 freq_counter_cmp; 123 u32 intr_ctrl; 124 u32 d2_pll_param; 125 u32 m_pll_param; 126 u32 h_pll_param; 127 u32 d_pll_param; 128 u32 misc_ctrl1; 129 u32 pci_config[3]; 130 u32 sysreset_status; 131 u32 vga_handshake[2]; 132 u32 mac_clk_delay; 133 u32 misc_ctrl2; 134 u32 vga_scratch[8]; 135 u32 hwstrap; 136 u32 rng_ctrl; 137 u32 rng_data; 138 u32 rev_id; 139 u32 pinmux_ctrl[6]; 140 u32 reserved0; 141 u32 extrst_sel; 142 u32 pinmux_ctrl1[4]; 143 u32 reserved1[2]; 144 u32 mac_clk_delay_100M; 145 u32 mac_clk_delay_10M; 146 u32 wakeup_enable; 147 u32 wakeup_control; 148 u32 reserved2[3]; 149 u32 sysreset_ctrl2; 150 u32 clk_sel2; 151 u32 clk_stop_ctrl2; 152 u32 freerun_counter; 153 u32 freerun_counter_ext; 154 u32 clk_duty_meas_ctrl; 155 u32 clk_duty_meas_res; 156 u32 reserved3[4]; 157 /* The next registers are not key-protected */ 158 struct ast2500_cpu2 { 159 u32 ctrl; 160 u32 base_addr[9]; 161 u32 cache_ctrl; 162 } cpu2; 163 u32 reserved4; 164 u32 d_pll_ext_param[3]; 165 u32 d2_pll_ext_param[3]; 166 u32 mh_pll_ext_param; 167 u32 reserved5; 168 u32 chip_id[2]; 169 u32 reserved6[2]; 170 u32 uart_clk_ctrl; 171 u32 reserved7[7]; 172 u32 pcie_config; 173 u32 mmio_decode; 174 u32 reloc_ctrl_decode[2]; 175 u32 mailbox_addr; 176 u32 shared_sram_decode[2]; 177 u32 bmc_rev_id; 178 u32 reserved8; 179 u32 bmc_device_id; 180 u32 reserved9[13]; 181 u32 clk_duty_sel; 182 }; 183 184 extern u32 ast2500_get_clkin(struct ast2500_scu *scu); 185 extern u32 ast2500_get_mpll_rate(struct ast2500_scu *scu); 186 extern u32 ast2500_get_hpll_rate(struct ast2500_scu *scu); 187 extern u32 ast2500_get_dpll_rate(struct ast2500_scu *scu); 188 extern u32 ast2500_get_d2pll_rate(struct ast2500_scu *scu); 189 190 191 192 #endif /* _ASM_ARCH_SCU_AST2500_H */ 193