1 /* 2 * Copyright (c) 2016 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_SCU_AST2500_H 7 #define _ASM_ARCH_SCU_AST2500_H 8 9 #define SCU_UNLOCK_VALUE 0x1688a8a8 10 11 #define SCU_HWSTRAP_VGAMEM_MASK 3 12 #define SCU_HWSTRAP_VGAMEM_SHIFT 2 13 #define SCU_HWSTRAP_DDR4 (1 << 24) 14 #define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23) 15 16 #define SCU_MPLL_DENUM_SHIFT 0 17 #define SCU_MPLL_DENUM_MASK 0x1f 18 #define SCU_MPLL_NUM_SHIFT 5 19 #define SCU_MPLL_NUM_MASK 0xff 20 #define SCU_MPLL_POST_SHIFT 13 21 #define SCU_MPLL_POST_MASK 0x3f 22 23 #define SCU_HPLL_DENUM_SHIFT 0 24 #define SCU_HPLL_DENUM_MASK 0x1f 25 #define SCU_HPLL_NUM_SHIFT 5 26 #define SCU_HPLL_NUM_MASK 0xff 27 #define SCU_HPLL_POST_SHIFT 13 28 #define SCU_HPLL_POST_MASK 0x3f 29 30 #define SCU_MISC2_UARTCLK_SHIFT 24 31 32 #define SCU_MISC_UARTCLK_DIV13 (1 << 12) 33 34 #ifndef __ASSEMBLY__ 35 36 struct ast2500_clk_priv { 37 struct ast2500_scu *scu; 38 }; 39 40 struct ast2500_scu { 41 u32 protection_key; 42 u32 sysreset_ctrl1; 43 u32 clk_sel1; 44 u32 clk_stop_ctrl1; 45 u32 freq_counter_ctrl; 46 u32 freq_counter_cmp; 47 u32 intr_ctrl; 48 u32 d2_pll_param; 49 u32 m_pll_param; 50 u32 h_pll_param; 51 u32 d_pll_param; 52 u32 misc_ctrl1; 53 u32 pci_config[3]; 54 u32 sysreset_status; 55 u32 vga_handshake[2]; 56 u32 mac_clk_delay; 57 u32 misc_ctrl2; 58 u32 vga_scratch[8]; 59 u32 hwstrap; 60 u32 rng_ctrl; 61 u32 rng_data; 62 u32 rev_id; 63 u32 pinmux_ctrl[6]; 64 u32 reserved0; 65 u32 extrst_sel; 66 u32 pinmux_ctrl1[4]; 67 u32 reserved1[2]; 68 u32 mac_clk_delay_100M; 69 u32 mac_clk_delay_10M; 70 u32 wakeup_enable; 71 u32 wakeup_control; 72 u32 reserved2[3]; 73 u32 sysreset_ctrl2; 74 u32 clk_sel2; 75 u32 clk_stop_ctrl2; 76 u32 freerun_counter; 77 u32 freerun_counter_ext; 78 u32 clk_duty_meas_ctrl; 79 u32 clk_duty_meas_res; 80 u32 reserved3[4]; 81 /* The next registers are not key-protected */ 82 struct ast2500_cpu2 { 83 u32 ctrl; 84 u32 base_addr[9]; 85 u32 cache_ctrl; 86 } cpu2; 87 u32 reserved4; 88 u32 d_pll_ext_param[3]; 89 u32 d2_pll_ext_param[3]; 90 u32 mh_pll_ext_param; 91 u32 reserved5; 92 u32 chip_id[2]; 93 u32 reserved6[2]; 94 u32 uart_clk_ctrl; 95 u32 reserved7[7]; 96 u32 pcie_config; 97 u32 mmio_decode; 98 u32 reloc_ctrl_decode[2]; 99 u32 mailbox_addr; 100 u32 shared_sram_decode[2]; 101 u32 bmc_rev_id; 102 u32 reserved8; 103 u32 bmc_device_id; 104 u32 reserved9[13]; 105 u32 clk_duty_sel; 106 }; 107 108 /** 109 * ast_get_clk() - get a pointer to Clock Driver 110 * 111 * @devp, OUT - pointer to Clock Driver 112 * @return zero on success, error code (< 0) otherwise. 113 */ 114 int ast_get_clk(struct udevice **devp); 115 116 /** 117 * ast_get_scu() - get a pointer to SCU registers 118 * 119 * @return pointer to struct ast2500_scu on success, ERR_PTR otherwise 120 */ 121 void *ast_get_scu(void); 122 123 #endif /* __ASSEMBLY__ */ 124 125 #endif /* _ASM_ARCH_SCU_AST2500_H */ 126