1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2016 Google, Inc 4 */ 5 #ifndef _ASM_ARCH_SCU_AST2500_H 6 #define _ASM_ARCH_SCU_AST2500_H 7 8 #define SCU_UNLOCK_VALUE 0x1688a8a8 9 10 #define SCU_HWSTRAP_VGAMEM_SHIFT 2 11 #define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT) 12 #define SCU_HWSTRAP_MAC1_RGMII (1 << 6) 13 #define SCU_HWSTRAP_MAC2_RGMII (1 << 7) 14 #define SCU_HWSTRAP_DDR4 (1 << 24) 15 #define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23) 16 17 #define SCU_MPLL_DENUM_SHIFT 0 18 #define SCU_MPLL_DENUM_MASK 0x1f 19 #define SCU_MPLL_NUM_SHIFT 5 20 #define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT) 21 #define SCU_MPLL_POST_SHIFT 13 22 #define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT) 23 #define SCU_PCLK_DIV_SHIFT 23 24 #define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT) 25 #define SCU_HPLL_DENUM_SHIFT 0 26 #define SCU_HPLL_DENUM_MASK 0x1f 27 #define SCU_HPLL_NUM_SHIFT 5 28 #define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT) 29 #define SCU_HPLL_POST_SHIFT 13 30 #define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT) 31 32 #define SCU_MACCLK_SHIFT 16 33 #define SCU_MACCLK_MASK (7 << SCU_MACCLK_SHIFT) 34 35 #define SCU_MISC2_RGMII_HPLL (1 << 23) 36 #define SCU_MISC2_RGMII_CLKDIV_SHIFT 20 37 #define SCU_MISC2_RGMII_CLKDIV_MASK (3 << SCU_MISC2_RGMII_CLKDIV_SHIFT) 38 #define SCU_MISC2_RMII_MPLL (1 << 19) 39 #define SCU_MISC2_RMII_CLKDIV_SHIFT 16 40 #define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT) 41 #define SCU_MISC2_UARTCLK_SHIFT 24 42 43 #define SCU_MISC_D2PLL_OFF (1 << 4) 44 #define SCU_MISC_UARTCLK_DIV13 (1 << 12) 45 #define SCU_MISC_GCRT_USB20CLK (1 << 21) 46 47 #define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT 0 48 #define SCU_MICDS_MAC1RGMII_TXDLY_MASK (0x3f\ 49 << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT) 50 #define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT 6 51 #define SCU_MICDS_MAC2RGMII_TXDLY_MASK (0x3f\ 52 << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT) 53 #define SCU_MICDS_MAC1RMII_RDLY_SHIFT 12 54 #define SCU_MICDS_MAC1RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT) 55 #define SCU_MICDS_MAC2RMII_RDLY_SHIFT 18 56 #define SCU_MICDS_MAC2RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT) 57 #define SCU_MICDS_MAC1RMII_TXFALL (1 << 24) 58 #define SCU_MICDS_MAC2RMII_TXFALL (1 << 25) 59 #define SCU_MICDS_RMII1_RCLKEN (1 << 29) 60 #define SCU_MICDS_RMII2_RCLKEN (1 << 30) 61 #define SCU_MICDS_RGMIIPLL (1 << 31) 62 63 64 65 /* Bits 16-27 in the register control pin functions for I2C devices 3-14 */ 66 #define SCU_PINMUX_CTRL5_I2C (1 << 16) 67 68 /* 69 * The values are grouped by function, not by register. 70 * They are actually scattered across multiple loosely related registers. 71 */ 72 #define SCU_PIN_FUN_MAC1_MDC (1 << 30) 73 #define SCU_PIN_FUN_MAC1_MDIO (1 << 31) 74 #define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0) 75 #define SCU_PIN_FUN_MAC2_MDIO (1 << 2) 76 #define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1) 77 #define SCU_PIN_FUN_SCL1 (1 << 12) 78 #define SCU_PIN_FUN_SCL2 (1 << 14) 79 #define SCU_PIN_FUN_SDA1 (1 << 13) 80 #define SCU_PIN_FUN_SDA2 (1 << 15) 81 82 #define SCU_D2PLL_EXT1_OFF (1 << 0) 83 #define SCU_D2PLL_EXT1_BYPASS (1 << 1) 84 #define SCU_D2PLL_EXT1_RESET (1 << 2) 85 #define SCU_D2PLL_EXT1_MODE_SHIFT 3 86 #define SCU_D2PLL_EXT1_MODE_MASK (3 << SCU_D2PLL_EXT1_MODE_SHIFT) 87 #define SCU_D2PLL_EXT1_PARAM_SHIFT 5 88 #define SCU_D2PLL_EXT1_PARAM_MASK (0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT) 89 90 #define SCU_D2PLL_NUM_SHIFT 0 91 #define SCU_D2PLL_NUM_MASK (0xff << SCU_D2PLL_NUM_SHIFT) 92 #define SCU_D2PLL_DENUM_SHIFT 8 93 #define SCU_D2PLL_DENUM_MASK (0x1f << SCU_D2PLL_DENUM_SHIFT) 94 #define SCU_D2PLL_POST_SHIFT 13 95 #define SCU_D2PLL_POST_MASK (0x3f << SCU_D2PLL_POST_SHIFT) 96 #define SCU_D2PLL_ODIV_SHIFT 19 97 #define SCU_D2PLL_ODIV_MASK (7 << SCU_D2PLL_ODIV_SHIFT) 98 #define SCU_D2PLL_SIC_SHIFT 22 99 #define SCU_D2PLL_SIC_MASK (0x1f << SCU_D2PLL_SIC_SHIFT) 100 #define SCU_D2PLL_SIP_SHIFT 27 101 #define SCU_D2PLL_SIP_MASK (0x1f << SCU_D2PLL_SIP_SHIFT) 102 103 #define SCU_CLKDUTY_DCLK_SHIFT 0 104 #define SCU_CLKDUTY_DCLK_MASK (0x3f << SCU_CLKDUTY_DCLK_SHIFT) 105 #define SCU_CLKDUTY_RGMII1TXCK_SHIFT 8 106 #define SCU_CLKDUTY_RGMII1TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII1TXCK_SHIFT) 107 #define SCU_CLKDUTY_RGMII2TXCK_SHIFT 16 108 #define SCU_CLKDUTY_RGMII2TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII2TXCK_SHIFT) 109 110 struct ast2500_clk_priv { 111 struct ast2500_scu *scu; 112 }; 113 114 struct ast2500_scu { 115 u32 protection_key; 116 u32 sysreset_ctrl1; 117 u32 clk_sel1; 118 u32 clk_stop_ctrl1; 119 u32 freq_counter_ctrl; 120 u32 freq_counter_cmp; 121 u32 intr_ctrl; 122 u32 d2_pll_param; 123 u32 m_pll_param; 124 u32 h_pll_param; 125 u32 d_pll_param; 126 u32 misc_ctrl1; 127 u32 pci_config[3]; 128 u32 sysreset_status; 129 u32 vga_handshake[2]; 130 u32 mac_clk_delay; 131 u32 misc_ctrl2; 132 u32 vga_scratch[8]; 133 u32 hwstrap; 134 u32 rng_ctrl; 135 u32 rng_data; 136 u32 rev_id; 137 u32 pinmux_ctrl[6]; 138 u32 reserved0; 139 u32 extrst_sel; 140 u32 pinmux_ctrl1[4]; 141 u32 reserved1[2]; 142 u32 mac_clk_delay_100M; 143 u32 mac_clk_delay_10M; 144 u32 wakeup_enable; 145 u32 wakeup_control; 146 u32 reserved2[3]; 147 u32 sysreset_ctrl2; 148 u32 clk_sel2; 149 u32 clk_stop_ctrl2; 150 u32 freerun_counter; 151 u32 freerun_counter_ext; 152 u32 clk_duty_meas_ctrl; 153 u32 clk_duty_meas_res; 154 u32 reserved3[4]; 155 /* The next registers are not key-protected */ 156 struct ast2500_cpu2 { 157 u32 ctrl; 158 u32 base_addr[9]; 159 u32 cache_ctrl; 160 } cpu2; 161 u32 reserved4; 162 u32 d_pll_ext_param[3]; 163 u32 d2_pll_ext_param[3]; 164 u32 mh_pll_ext_param; 165 u32 reserved5; 166 u32 chip_id[2]; 167 u32 reserved6[2]; 168 u32 uart_clk_ctrl; 169 u32 reserved7[7]; 170 u32 pcie_config; 171 u32 mmio_decode; 172 u32 reloc_ctrl_decode[2]; 173 u32 mailbox_addr; 174 u32 shared_sram_decode[2]; 175 u32 bmc_rev_id; 176 u32 reserved8; 177 u32 bmc_device_id; 178 u32 reserved9[13]; 179 u32 clk_duty_sel; 180 }; 181 182 #endif /* _ASM_ARCH_SCU_AST2500_H */ 183