1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 #ifndef _ASM_ARCH_SCU_AST2400_H 3 #define _ASM_ARCH_SCU_AST2400_H 4 5 #define SCU_UNLOCK_VALUE 0x1688a8a8 6 7 #define SCU_HWSTRAP_VGAMEM_SHIFT 2 8 #define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT) 9 #define SCU_HWSTRAP_MAC1_RGMII (1 << 6) 10 #define SCU_HWSTRAP_MAC2_RGMII (1 << 7) 11 #define SCU_HWSTRAP_LPC_SIO_DEC_DIS (1 << 20) 12 #define SCU_HWSTRAP_DDR4 (1 << 24) 13 #define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23) 14 15 #define SCU_MPLL_DENUM_SHIFT 0 16 #define SCU_MPLL_DENUM_MASK 0x1f 17 #define SCU_MPLL_NUM_SHIFT 5 18 #define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT) 19 #define SCU_MPLL_POST_SHIFT 13 20 #define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT) 21 #define SCU_PCLK_DIV_SHIFT 23 22 #define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT) 23 #define SCU_HPLL_DENUM_SHIFT 0 24 #define SCU_HPLL_DENUM_MASK 0x1f 25 #define SCU_HPLL_NUM_SHIFT 5 26 #define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT) 27 #define SCU_HPLL_POST_SHIFT 13 28 #define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT) 29 30 #define SCU_MACCLK_SHIFT 16 31 #define SCU_MACCLK_MASK (7 << SCU_MACCLK_SHIFT) 32 33 #define SCU_MISC2_RGMII_HPLL (1 << 23) 34 #define SCU_MISC2_RGMII_CLKDIV_SHIFT 20 35 #define SCU_MISC2_RGMII_CLKDIV_MASK (3 << SCU_MISC2_RGMII_CLKDIV_SHIFT) 36 #define SCU_MISC2_RMII_MPLL (1 << 19) 37 #define SCU_MISC2_RMII_CLKDIV_SHIFT 16 38 #define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT) 39 #define SCU_MISC2_UARTCLK_SHIFT 24 40 41 #define SCU_MISC_D2PLL_OFF (1 << 4) 42 #define SCU_MISC_UARTCLK_DIV13 (1 << 12) 43 #define SCU_MISC_GCRT_USB20CLK (1 << 21) 44 45 #define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT 0 46 #define SCU_MICDS_MAC1RGMII_TXDLY_MASK (0x3f\ 47 << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT) 48 #define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT 6 49 #define SCU_MICDS_MAC2RGMII_TXDLY_MASK (0x3f\ 50 << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT) 51 #define SCU_MICDS_MAC1RMII_RDLY_SHIFT 12 52 #define SCU_MICDS_MAC1RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT) 53 #define SCU_MICDS_MAC2RMII_RDLY_SHIFT 18 54 #define SCU_MICDS_MAC2RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT) 55 #define SCU_MICDS_MAC1RMII_TXFALL (1 << 24) 56 #define SCU_MICDS_MAC2RMII_TXFALL (1 << 25) 57 #define SCU_MICDS_RMII1_RCLKEN (1 << 29) 58 #define SCU_MICDS_RMII2_RCLKEN (1 << 30) 59 #define SCU_MICDS_RGMIIPLL (1 << 31) 60 61 62 63 /* Bits 16-27 in the register control pin functions for I2C devices 3-14 */ 64 #define SCU_PINMUX_CTRL5_I2C (1 << 16) 65 66 /* 67 * The values are grouped by function, not by register. 68 * They are actually scattered across multiple loosely related registers. 69 */ 70 #define SCU_PIN_FUN_MAC1_MDC (1 << 30) 71 #define SCU_PIN_FUN_MAC1_MDIO (1 << 31) 72 #define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0) 73 #define SCU_PIN_FUN_MAC2_MDIO (1 << 2) 74 #define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1) 75 #define SCU_PIN_FUN_SCL1 (1 << 12) 76 #define SCU_PIN_FUN_SCL2 (1 << 14) 77 #define SCU_PIN_FUN_SDA1 (1 << 13) 78 #define SCU_PIN_FUN_SDA2 (1 << 15) 79 80 #define SCU_D2PLL_EXT1_OFF (1 << 0) 81 #define SCU_D2PLL_EXT1_BYPASS (1 << 1) 82 #define SCU_D2PLL_EXT1_RESET (1 << 2) 83 #define SCU_D2PLL_EXT1_MODE_SHIFT 3 84 #define SCU_D2PLL_EXT1_MODE_MASK (3 << SCU_D2PLL_EXT1_MODE_SHIFT) 85 #define SCU_D2PLL_EXT1_PARAM_SHIFT 5 86 #define SCU_D2PLL_EXT1_PARAM_MASK (0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT) 87 88 #define SCU_D2PLL_NUM_SHIFT 0 89 #define SCU_D2PLL_NUM_MASK (0xff << SCU_D2PLL_NUM_SHIFT) 90 #define SCU_D2PLL_DENUM_SHIFT 8 91 #define SCU_D2PLL_DENUM_MASK (0x1f << SCU_D2PLL_DENUM_SHIFT) 92 #define SCU_D2PLL_POST_SHIFT 13 93 #define SCU_D2PLL_POST_MASK (0x3f << SCU_D2PLL_POST_SHIFT) 94 #define SCU_D2PLL_ODIV_SHIFT 19 95 #define SCU_D2PLL_ODIV_MASK (7 << SCU_D2PLL_ODIV_SHIFT) 96 #define SCU_D2PLL_SIC_SHIFT 22 97 #define SCU_D2PLL_SIC_MASK (0x1f << SCU_D2PLL_SIC_SHIFT) 98 #define SCU_D2PLL_SIP_SHIFT 27 99 #define SCU_D2PLL_SIP_MASK (0x1f << SCU_D2PLL_SIP_SHIFT) 100 101 #define SCU_CLKDUTY_DCLK_SHIFT 0 102 #define SCU_CLKDUTY_DCLK_MASK (0x3f << SCU_CLKDUTY_DCLK_SHIFT) 103 #define SCU_CLKDUTY_RGMII1TXCK_SHIFT 8 104 #define SCU_CLKDUTY_RGMII1TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII1TXCK_SHIFT) 105 #define SCU_CLKDUTY_RGMII2TXCK_SHIFT 16 106 #define SCU_CLKDUTY_RGMII2TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII2TXCK_SHIFT) 107 108 #define SCU_PCIE_CONFIG_SET_VGA_MMIO (1 << 1) 109 #define SCU_PCIE_CONFIG_SET_BMC_EN (1 << 8) 110 #define SCU_PCIE_CONFIG_SET_BMC_MMIO (1 << 9) 111 #define SCU_PCIE_CONFIG_SET_BMC_DMA (1 << 14) 112 113 114 struct ast2400_clk_priv { 115 struct ast2400_scu *scu; 116 }; 117 118 struct ast2400_scu { 119 u32 protection_key; /* 0x00 */ 120 u32 sysreset_ctrl1; /* 0x04 */ 121 u32 clk_sel1; /* 0x08 */ 122 u32 clk_stop_ctrl1; /* 0x0C */ 123 u32 freq_counter_ctrl; /* 0x10 */ 124 u32 freq_counter_measure; /* 0x14 */ 125 u32 intr_ctrl; /* 0x18 */ 126 u32 d2_pll_param; /* 0x1C */ 127 u32 m_pll_param; /* 0x20 */ 128 u32 h_pll_param; /* 0x24 */ 129 u32 freq_counter_cmp; /* 0x28 */ 130 u32 misc_ctrl1; /* 0x2C */ 131 u32 pci_config[3]; /* 0x30 */ 132 u32 sysreset_status; /* 0x3C */ 133 u32 vga_handshake[2]; /* 0x40 */ 134 u32 mac_clk_delay; /* 0x48 */ 135 u32 misc_ctrl2; /* 0x4C */ 136 u32 vga_scratch[8]; /* 0x50 */ 137 u32 hwstrap; /* 0x70 */ 138 u32 rng_ctrl; /* 0x74 */ 139 u32 rng_data; /* 0x78 */ 140 u32 rev_id; /* 0x7C */ 141 u32 pinmux_ctrl[6]; /* 0x80 */ 142 u32 reserved0; /* 0x98 */ 143 u32 wdt_rst_sel; /* 0x9C */ 144 u32 pinmux_ctrl1[3]; /* 0xA0 */ 145 u32 reserved1[5]; /* 0xAC */ 146 u32 wakeup_enable; /* 0xC0 */ 147 u32 wakeup_control; /* 0xC4 */ 148 u32 reserved2[2]; /* 0xC8 */ 149 u32 hwstrap2; /* 0xD0 */ 150 u32 reserved3[3]; /* 0xD4 */ 151 u32 freerun_counter; /* 0xE0 */ 152 u32 freerun_counter_ext; /* 0xE4 */ 153 //E8/EC 154 //F0/F4/F8/FC 155 u32 reserved4[6]; /* 0xE8 */ 156 /* The next registers are not key-protected */ 157 struct ast2400_cpu2 { /* 0x100 */ 158 u32 ctrl; 159 u32 base_addr[5]; 160 u32 cache_ctrl; 161 } cpu2; 162 u32 reserved5[17]; /* 0x11C */ 163 //11C/ 164 //120/124/128/12c 165 //130/134/138/13c 166 //140/144/148/14c 167 //150/154/158/15c 168 u32 uart_clk_ctrl; /* 0x160 */ 169 u32 reserved7[7]; 170 u32 pcie_config; /* 0x180 */ 171 u32 mmio_decode; 172 u32 reloc_ctrl_decode[2]; 173 u32 mailbox_addr; 174 u32 shared_sram_decode[2]; 175 u32 bmc_rev_id; 176 u32 reserved8; 177 u32 bmc_device_id; 178 u32 reserved9[13]; 179 u32 clk_duty_sel; 180 }; 181 182 #endif /* _ASM_ARCH_SCU_AST2400_H */ 183