1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * Ryan Chen <ryan_chen@aspeedtech.com> 5 * 6 */ 7 8 #ifndef _ASPEED_PLATFORM_H_ 9 #define _ASPEED_PLATFORM_H_ 10 11 #define AST_PLL_25MHZ 25000000 12 #define AST_PLL_24MHZ 24000000 13 #define AST_PLL_12MHZ 12000000 14 15 /*********************************************************************************/ 16 #if defined(CONFIG_ASPEED_AST2400) 17 #define ASPEED_MAC_COUNT 2 18 #define ASPEED_HW_STRAP1 0x1e6e2070 19 #define ASPEED_REVISION_ID 0x1e6e207C 20 #define ASPEED_SYS_RESET_CTRL 0x1e6e203C 21 #define ASPEED_VGA_HANDSHAKE0 0x1e6e2040 /* VGA fuction handshake register */ 22 #define ASPEED_DRAM_BASE 0x40000000 23 #define ASPEED_SRAM_BASE 0x1E720000 24 #define ASPEED_SRAM_SIZE 0x9000 25 #define ASPEED_FMC_CS0_BASE 0x20000000 26 #elif defined(CONFIG_ASPEED_AST2500) 27 #define ASPEED_MAC_COUNT 2 28 #define ASPEED_HW_STRAP1 0x1e6e2070 29 #define ASPEED_HW_STRAP2 0x1e6e20D0 30 #define ASPEED_REVISION_ID 0x1e6e207C 31 #define ASPEED_SYS_RESET_CTRL 0x1e6e203C 32 #define ASPEED_VGA_HANDSHAKE0 0x1e6e2040 /* VGA fuction handshake register */ 33 #define ASPEED_MAC_COUNT 2 34 #define ASPEED_DRAM_BASE 0x80000000 35 #define ASPEED_SRAM_BASE 0x1E720000 36 #define ASPEED_SRAM_SIZE 0x9000 37 #define ASPEED_FMC_CS0_BASE 0x20000000 38 #elif defined(CONFIG_ASPEED_AST2600) 39 #define ASPEED_HW_STRAP1 0x1e6e2500 40 #define ASPEED_HW_STRAP2 0x1e6e2510 41 #define ASPEED_REVISION_ID 0x1e6e2004 42 #define ASPEED_SYS_RESET_CTRL 0x1e6e2064 43 #define ASPEED_SYS_RESET_CTRL3 0x1e6e206c 44 #define ASPEED_VGA_HANDSHAKE0 0x1e6e2100 /* VGA fuction handshake register */ 45 #define ASPEED_MAC_COUNT 4 46 #define ASPEED_DRAM_BASE 0x80000000 47 #define ASPEED_SRAM_BASE 0x10000000 48 #define ASPEED_SRAM_SIZE 0x10000 49 #define ASPEED_FMC_CS0_BASE 0x20000000 50 #else 51 #err "No define for platform.h" 52 #endif 53 54 #endif 55