1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2b80e41acSMatt Waddel /* 3b80e41acSMatt Waddel * (C) Copyright 2010 Linaro 4b80e41acSMatt Waddel * Matt Waddel, <matt.waddel@linaro.org> 5b80e41acSMatt Waddel */ 6b80e41acSMatt Waddel #ifndef _SYSTIMER_H_ 7b80e41acSMatt Waddel #define _SYSTIMER_H_ 8b80e41acSMatt Waddel 9b80e41acSMatt Waddel /* AMBA timer register base address */ 10b80e41acSMatt Waddel #define SYSTIMER_BASE 0x10011000 11b80e41acSMatt Waddel 12b80e41acSMatt Waddel #define SYSHZ_CLOCK 1000000 /* Timers -> 1Mhz */ 13b80e41acSMatt Waddel #define SYSTIMER_RELOAD 0xFFFFFFFF 14b80e41acSMatt Waddel #define SYSTIMER_EN (1 << 7) 15b80e41acSMatt Waddel #define SYSTIMER_32BIT (1 << 1) 16714d1f5dSRob Herring #define SYSTIMER_PRESC_16 (1 << 2) 17714d1f5dSRob Herring #define SYSTIMER_PRESC_256 (1 << 3) 18b80e41acSMatt Waddel 19b80e41acSMatt Waddel struct systimer { 20b80e41acSMatt Waddel u32 timer0load; /* 0x00 */ 21b80e41acSMatt Waddel u32 timer0value; 22b80e41acSMatt Waddel u32 timer0control; 23b80e41acSMatt Waddel u32 timer0intclr; 24b80e41acSMatt Waddel u32 timer0ris; 25b80e41acSMatt Waddel u32 timer0mis; 26b80e41acSMatt Waddel u32 timer0bgload; 27b80e41acSMatt Waddel u32 timer1load; /* 0x20 */ 28b80e41acSMatt Waddel u32 timer1value; 29b80e41acSMatt Waddel u32 timer1control; 30b80e41acSMatt Waddel u32 timer1intclr; 31b80e41acSMatt Waddel u32 timer1ris; 32b80e41acSMatt Waddel u32 timer1mis; 33b80e41acSMatt Waddel u32 timer1bgload; 34b80e41acSMatt Waddel }; 35b80e41acSMatt Waddel #endif /* _SYSTIMER_H_ */ 36