1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2012
4  * eInfochips Ltd. <www.einfochips.com>
5  * Written-by: Ajay Bhargav <contact@8051projects.net>
6  *
7  * (C) Copyright 2009
8  * Marvell Semiconductor <www.marvell.com>
9  */
10 
11 #ifndef __UTMI_ARMADA100__
12 #define __UTMI_ARMADA100__
13 
14 #define UTMI_PHY_BASE		0xD4206000
15 
16 /* utmi_ctrl - bits */
17 #define INPKT_DELAY_SOF		(1 << 28)
18 #define PLL_PWR_UP		2
19 #define PHY_PWR_UP		1
20 
21 /* utmi_pll - bits */
22 #define PLL_FBDIV_MASK		0x00000FF0
23 #define PLL_FBDIV		4
24 #define PLL_REFDIV_MASK		0x0000000F
25 #define PLL_REFDIV		0
26 #define PLL_READY		0x800000
27 #define VCOCAL_START		(1 << 21)
28 
29 #define N_DIVIDER		0xEE
30 #define M_DIVIDER		0x0B
31 
32 /* utmi_tx - bits */
33 #define CK60_PHSEL		17
34 #define PHSEL_VAL		0x4
35 #define RCAL_START		(1 << 12)
36 
37 /*
38  * USB PHY registers
39  * Refer Datasheet Appendix A.21
40  */
41 struct armd1usb_phy_reg {
42 	u32 utmi_rev;	/* USB PHY Revision */
43 	u32 utmi_ctrl;	/* USB PHY Control register */
44 	u32 utmi_pll;	/* PLL register */
45 	u32 utmi_tx;	/* Tx register */
46 	u32 utmi_rx;	/* Rx register */
47 	u32 utmi_ivref;	/* IVREF register */
48 	u32 utmi_tst_g0;	/* Test group 0 register */
49 	u32 utmi_tst_g1;	/* Test group 1 register */
50 	u32 utmi_tst_g2;	/* Test group 2 register */
51 	u32 utmi_tst_g3;	/* Test group 3 register */
52 	u32 utmi_tst_g4;	/* Test group 4 register */
53 	u32 utmi_tst_g5;	/* Test group 5 register */
54 	u32 utmi_reserve;	/* Reserve Register */
55 	u32 utmi_usb_int;	/* USB interuppt register */
56 	u32 utmi_dbg_ctl;	/* Debug control register */
57 	u32 utmi_otg_addon;	/* OTG addon register */
58 };
59 
60 int utmi_init(void);
61 
62 #endif /* __UTMI_ARMADA100__ */
63