1 /* 2 * (C) Copyright 2012 3 * eInfochips Ltd. <www.einfochips.com> 4 * Written-by: Ajay Bhargav <contact@8051projects.net> 5 * 6 * (C) Copyright 2009 7 * Marvell Semiconductor <www.marvell.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __UTMI_ARMADA100__ 13 #define __UTMI_ARMADA100__ 14 15 #define UTMI_PHY_BASE 0xD4206000 16 17 /* utmi_ctrl - bits */ 18 #define INPKT_DELAY_SOF (1 << 28) 19 #define PLL_PWR_UP 2 20 #define PHY_PWR_UP 1 21 22 /* utmi_pll - bits */ 23 #define PLL_FBDIV_MASK 0x00000FF0 24 #define PLL_FBDIV 4 25 #define PLL_REFDIV_MASK 0x0000000F 26 #define PLL_REFDIV 0 27 #define PLL_READY 0x800000 28 #define VCOCAL_START (1 << 21) 29 30 #define N_DIVIDER 0xEE 31 #define M_DIVIDER 0x0B 32 33 /* utmi_tx - bits */ 34 #define CK60_PHSEL 17 35 #define PHSEL_VAL 0x4 36 #define RCAL_START (1 << 12) 37 38 /* 39 * USB PHY registers 40 * Refer Datasheet Appendix A.21 41 */ 42 struct armd1usb_phy_reg { 43 u32 utmi_rev; /* USB PHY Revision */ 44 u32 utmi_ctrl; /* USB PHY Control register */ 45 u32 utmi_pll; /* PLL register */ 46 u32 utmi_tx; /* Tx register */ 47 u32 utmi_rx; /* Rx register */ 48 u32 utmi_ivref; /* IVREF register */ 49 u32 utmi_tst_g0; /* Test group 0 register */ 50 u32 utmi_tst_g1; /* Test group 1 register */ 51 u32 utmi_tst_g2; /* Test group 2 register */ 52 u32 utmi_tst_g3; /* Test group 3 register */ 53 u32 utmi_tst_g4; /* Test group 4 register */ 54 u32 utmi_tst_g5; /* Test group 5 register */ 55 u32 utmi_reserve; /* Reserve Register */ 56 u32 utmi_usb_int; /* USB interuppt register */ 57 u32 utmi_dbg_ctl; /* Debug control register */ 58 u32 utmi_otg_addon; /* OTG addon register */ 59 }; 60 61 int utmi_init(void); 62 63 #endif /* __UTMI_ARMADA100__ */ 64