1 /* 2 * (C) Copyright 2012 3 * eInfochips Ltd. <www.einfochips.com> 4 * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com> 5 * 6 * (C) Copyright 2009 7 * Marvell Semiconductor <www.marvell.com> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 25 * MA 02110-1301 USA 26 */ 27 28 #ifndef __UTMI_ARMADA100__ 29 #define __UTMI_ARMADA100__ 30 31 #define UTMI_PHY_BASE 0xD4206000 32 33 /* utmi_ctrl - bits */ 34 #define INPKT_DELAY_SOF (1 << 28) 35 #define PLL_PWR_UP 2 36 #define PHY_PWR_UP 1 37 38 /* utmi_pll - bits */ 39 #define PLL_FBDIV_MASK 0x00000FF0 40 #define PLL_FBDIV 4 41 #define PLL_REFDIV_MASK 0x0000000F 42 #define PLL_REFDIV 0 43 #define PLL_READY 0x800000 44 #define VCOCAL_START (1 << 21) 45 46 #define N_DIVIDER 0xEE 47 #define M_DIVIDER 0x0B 48 49 /* utmi_tx - bits */ 50 #define CK60_PHSEL 17 51 #define PHSEL_VAL 0x4 52 #define RCAL_START (1 << 12) 53 54 /* 55 * USB PHY registers 56 * Refer Datasheet Appendix A.21 57 */ 58 struct armd1usb_phy_reg { 59 u32 utmi_rev; /* USB PHY Revision */ 60 u32 utmi_ctrl; /* USB PHY Control register */ 61 u32 utmi_pll; /* PLL register */ 62 u32 utmi_tx; /* Tx register */ 63 u32 utmi_rx; /* Rx register */ 64 u32 utmi_ivref; /* IVREF register */ 65 u32 utmi_tst_g0; /* Test group 0 register */ 66 u32 utmi_tst_g1; /* Test group 1 register */ 67 u32 utmi_tst_g2; /* Test group 2 register */ 68 u32 utmi_tst_g3; /* Test group 3 register */ 69 u32 utmi_tst_g4; /* Test group 4 register */ 70 u32 utmi_tst_g5; /* Test group 5 register */ 71 u32 utmi_reserve; /* Reserve Register */ 72 u32 utmi_usb_int; /* USB interuppt register */ 73 u32 utmi_dbg_ctl; /* Debug control register */ 74 u32 utmi_otg_addon; /* OTG addon register */ 75 }; 76 77 int utmi_init(void); 78 79 #endif /* __UTMI_ARMADA100__ */ 80