1 /* 2 * (C) Copyright 2010 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 */ 24 25 #ifndef _ARMADA100CPU_H 26 #define _ARMADA100CPU_H 27 28 #include <asm/io.h> 29 #include <asm/system.h> 30 31 /* 32 * Main Power Management (MPMU) Registers 33 * Refer Datasheet Appendix A.8 34 */ 35 struct armd1mpmu_registers { 36 u8 pad0[0x08 - 0x00]; 37 u32 fccr; /*0x0008*/ 38 u32 pocr; /*0x000c*/ 39 u32 posr; /*0x0010*/ 40 u32 succr; /*0x0014*/ 41 u8 pad1[0x030 - 0x014 - 4]; 42 u32 gpcr; /*0x0030*/ 43 u8 pad2[0x200 - 0x030 - 4]; 44 u32 wdtpcr; /*0x0200*/ 45 u8 pad3[0x1000 - 0x200 - 4]; 46 u32 apcr; /*0x1000*/ 47 u32 apsr; /*0x1004*/ 48 u8 pad4[0x1020 - 0x1004 - 4]; 49 u32 aprr; /*0x1020*/ 50 u32 acgr; /*0x1024*/ 51 u32 arsr; /*0x1028*/ 52 }; 53 54 /* 55 * Application Subsystem Power Management 56 * Refer Datasheet Appendix A.9 57 */ 58 struct armd1apmu_registers { 59 u32 pcr; /* 0x000 */ 60 u32 ccr; /* 0x004 */ 61 u32 pad1; 62 u32 ccsr; /* 0x00C */ 63 u32 fc_timer; /* 0x010 */ 64 u32 pad2; 65 u32 ideal_cfg; /* 0x018 */ 66 u8 pad3[0x04C - 0x018 - 4]; 67 u32 lcdcrc; /* 0x04C */ 68 u32 cciccrc; /* 0x050 */ 69 u32 sd1crc; /* 0x054 */ 70 u32 sd2crc; /* 0x058 */ 71 u32 usbcrc; /* 0x05C */ 72 u32 nfccrc; /* 0x060 */ 73 u32 dmacrc; /* 0x064 */ 74 u32 pad4; 75 u32 buscrc; /* 0x06C */ 76 u8 pad5[0x07C - 0x06C - 4]; 77 u32 wake_clr; /* 0x07C */ 78 u8 pad6[0x090 - 0x07C - 4]; 79 u32 core_status; /* 0x090 */ 80 u32 rfsc; /* 0x094 */ 81 u32 imr; /* 0x098 */ 82 u32 irwc; /* 0x09C */ 83 u32 isr; /* 0x0A0 */ 84 u8 pad7[0x0B0 - 0x0A0 - 4]; 85 u32 mhst; /* 0x0B0 */ 86 u32 msr; /* 0x0B4 */ 87 u8 pad8[0x0C0 - 0x0B4 - 4]; 88 u32 msst; /* 0x0C0 */ 89 u32 pllss; /* 0x0C4 */ 90 u32 smb; /* 0x0C8 */ 91 u32 gccrc; /* 0x0CC */ 92 u8 pad9[0x0D4 - 0x0CC - 4]; 93 u32 smccrc; /* 0x0D4 */ 94 u32 pad10; 95 u32 xdcrc; /* 0x0DC */ 96 u32 sd3crc; /* 0x0E0 */ 97 u32 sd4crc; /* 0x0E4 */ 98 u8 pad11[0x0F0 - 0x0E4 - 4]; 99 u32 cfcrc; /* 0x0F0 */ 100 u32 mspcrc; /* 0x0F4 */ 101 u32 cmucrc; /* 0x0F8 */ 102 u32 fecrc; /* 0x0FC */ 103 u32 pciecrc; /* 0x100 */ 104 u32 epdcrc; /* 0x104 */ 105 }; 106 107 /* 108 * APB1 Clock Reset/Control Registers 109 * Refer Datasheet Appendix A.10 110 */ 111 struct armd1apb1_registers { 112 u32 uart1; /*0x000*/ 113 u32 uart2; /*0x004*/ 114 u32 gpio; /*0x008*/ 115 u32 pwm1; /*0x00c*/ 116 u32 pwm2; /*0x010*/ 117 u32 pwm3; /*0x014*/ 118 u32 pwm4; /*0x018*/ 119 u8 pad0[0x028 - 0x018 - 4]; 120 u32 rtc; /*0x028*/ 121 u32 twsi0; /*0x02c*/ 122 u32 kpc; /*0x030*/ 123 u32 timers; /*0x034*/ 124 u8 pad1[0x03c - 0x034 - 4]; 125 u32 aib; /*0x03c*/ 126 u32 sw_jtag; /*0x040*/ 127 u32 timer1; /*0x044*/ 128 u32 onewire; /*0x048*/ 129 u8 pad2[0x050 - 0x048 - 4]; 130 u32 asfar; /*0x050 AIB Secure First Access Reg*/ 131 u32 assar; /*0x054 AIB Secure Second Access Reg*/ 132 u8 pad3[0x06c - 0x054 - 4]; 133 u32 twsi1; /*0x06c*/ 134 u32 uart3; /*0x070*/ 135 u8 pad4[0x07c - 0x070 - 4]; 136 u32 timer2; /*0x07C*/ 137 u8 pad5[0x084 - 0x07c - 4]; 138 u32 ac97; /*0x084*/ 139 }; 140 141 /* 142 * APB2 Clock Reset/Control Registers 143 * Refer Datasheet Appendix A.11 144 */ 145 struct armd1apb2_registers { 146 u32 pad1[0x01C - 0x000]; 147 u32 ssp1_clkrst; /* 0x01C */ 148 u32 ssp2_clkrst; /* 0x020 */ 149 u32 pad2[0x04C - 0x020 - 4]; 150 u32 ssp3_clkrst; /* 0x04C */ 151 u32 pad3[0x058 - 0x04C - 4]; 152 u32 ssp4_clkrst; /* 0x058 */ 153 u32 ssp5_clkrst; /* 0x05C */ 154 }; 155 156 /* 157 * CPU Interface Registers 158 * Refer Datasheet Appendix A.2 159 */ 160 struct armd1cpu_registers { 161 u32 chip_id; /* Chip Id Reg */ 162 u32 pad; 163 u32 cpu_conf; /* CPU Conf Reg */ 164 u32 pad1; 165 u32 cpu_sram_spd; /* CPU SRAM Speed Reg */ 166 u32 pad2; 167 u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */ 168 u32 mcb_conf; /* MCB Conf Reg */ 169 u32 sys_boot_ctl; /* Sytem Boot Control */ 170 }; 171 172 /* 173 * Functions 174 */ 175 u32 armd1_sdram_base(int); 176 u32 armd1_sdram_size(int); 177 178 #endif /* _ARMADA100CPU_H */ 179