1 /* 2 * (C) Copyright 2010 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5 * Contributor: Mahavir Jain <mjain@marvell.com> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 23 * MA 02110-1301 USA 24 */ 25 26 #ifndef _ASM_ARCH_ARMADA100_H 27 #define _ASM_ARCH_ARMADA100_H 28 29 #ifndef __ASSEMBLY__ 30 #include <asm/types.h> 31 #include <asm/io.h> 32 #endif /* __ASSEMBLY__ */ 33 34 #if defined (CONFIG_ARMADA100) 35 #include <asm/arch/cpu.h> 36 37 /* Common APB clock register bit definitions */ 38 #define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */ 39 #define APBC_FNCLK (1<<1) /* Functional Clock Enable */ 40 #define APBC_RST (1<<2) /* Reset Generation */ 41 /* Functional Clock Selection Mask */ 42 #define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) 43 44 /* Fast Ethernet Controller Clock register definition */ 45 #define FE_CLK_RST 0x1 46 #define FE_CLK_ENA 0x8 47 48 /* Register Base Addresses */ 49 #define ARMD1_DRAM_BASE 0xB0000000 50 #define ARMD1_FEC_BASE 0xC0800000 51 #define ARMD1_TIMER_BASE 0xD4014000 52 #define ARMD1_APBC1_BASE 0xD4015000 53 #define ARMD1_APBC2_BASE 0xD4015800 54 #define ARMD1_UART1_BASE 0xD4017000 55 #define ARMD1_UART2_BASE 0xD4018000 56 #define ARMD1_GPIO_BASE 0xD4019000 57 #define ARMD1_SSP1_BASE 0xD401B000 58 #define ARMD1_SSP2_BASE 0xD401C000 59 #define ARMD1_MFPR_BASE 0xD401E000 60 #define ARMD1_SSP3_BASE 0xD401F000 61 #define ARMD1_SSP4_BASE 0xD4020000 62 #define ARMD1_SSP5_BASE 0xD4021000 63 #define ARMD1_UART3_BASE 0xD4026000 64 #define ARMD1_MPMU_BASE 0xD4050000 65 #define ARMD1_APMU_BASE 0xD4282800 66 #define ARMD1_CPU_BASE 0xD4282C00 67 68 /* 69 * Main Power Management (MPMU) Registers 70 * Refer Datasheet Appendix A.8 71 */ 72 struct armd1mpmu_registers { 73 u8 pad0[0x08 - 0x00]; 74 u32 fccr; /*0x0008*/ 75 u32 pocr; /*0x000c*/ 76 u32 posr; /*0x0010*/ 77 u32 succr; /*0x0014*/ 78 u8 pad1[0x030 - 0x014 - 4]; 79 u32 gpcr; /*0x0030*/ 80 u8 pad2[0x200 - 0x030 - 4]; 81 u32 wdtpcr; /*0x0200*/ 82 u8 pad3[0x1000 - 0x200 - 4]; 83 u32 apcr; /*0x1000*/ 84 u32 apsr; /*0x1004*/ 85 u8 pad4[0x1020 - 0x1004 - 4]; 86 u32 aprr; /*0x1020*/ 87 u32 acgr; /*0x1024*/ 88 u32 arsr; /*0x1028*/ 89 }; 90 91 /* 92 * Application Subsystem Power Management 93 * Refer Datasheet Appendix A.9 94 */ 95 struct armd1apmu_registers { 96 u32 pcr; /* 0x000 */ 97 u32 ccr; /* 0x004 */ 98 u32 pad1; 99 u32 ccsr; /* 0x00C */ 100 u32 fc_timer; /* 0x010 */ 101 u32 pad2; 102 u32 ideal_cfg; /* 0x018 */ 103 u8 pad3[0x04C - 0x018 - 4]; 104 u32 lcdcrc; /* 0x04C */ 105 u32 cciccrc; /* 0x050 */ 106 u32 sd1crc; /* 0x054 */ 107 u32 sd2crc; /* 0x058 */ 108 u32 usbcrc; /* 0x05C */ 109 u32 nfccrc; /* 0x060 */ 110 u32 dmacrc; /* 0x064 */ 111 u32 pad4; 112 u32 buscrc; /* 0x06C */ 113 u8 pad5[0x07C - 0x06C - 4]; 114 u32 wake_clr; /* 0x07C */ 115 u8 pad6[0x090 - 0x07C - 4]; 116 u32 core_status; /* 0x090 */ 117 u32 rfsc; /* 0x094 */ 118 u32 imr; /* 0x098 */ 119 u32 irwc; /* 0x09C */ 120 u32 isr; /* 0x0A0 */ 121 u8 pad7[0x0B0 - 0x0A0 - 4]; 122 u32 mhst; /* 0x0B0 */ 123 u32 msr; /* 0x0B4 */ 124 u8 pad8[0x0C0 - 0x0B4 - 4]; 125 u32 msst; /* 0x0C0 */ 126 u32 pllss; /* 0x0C4 */ 127 u32 smb; /* 0x0C8 */ 128 u32 gccrc; /* 0x0CC */ 129 u8 pad9[0x0D4 - 0x0CC - 4]; 130 u32 smccrc; /* 0x0D4 */ 131 u32 pad10; 132 u32 xdcrc; /* 0x0DC */ 133 u32 sd3crc; /* 0x0E0 */ 134 u32 sd4crc; /* 0x0E4 */ 135 u8 pad11[0x0F0 - 0x0E4 - 4]; 136 u32 cfcrc; /* 0x0F0 */ 137 u32 mspcrc; /* 0x0F4 */ 138 u32 cmucrc; /* 0x0F8 */ 139 u32 fecrc; /* 0x0FC */ 140 u32 pciecrc; /* 0x100 */ 141 u32 epdcrc; /* 0x104 */ 142 }; 143 144 /* 145 * APB1 Clock Reset/Control Registers 146 * Refer Datasheet Appendix A.10 147 */ 148 struct armd1apb1_registers { 149 u32 uart1; /*0x000*/ 150 u32 uart2; /*0x004*/ 151 u32 gpio; /*0x008*/ 152 u32 pwm1; /*0x00c*/ 153 u32 pwm2; /*0x010*/ 154 u32 pwm3; /*0x014*/ 155 u32 pwm4; /*0x018*/ 156 u8 pad0[0x028 - 0x018 - 4]; 157 u32 rtc; /*0x028*/ 158 u32 twsi0; /*0x02c*/ 159 u32 kpc; /*0x030*/ 160 u32 timers; /*0x034*/ 161 u8 pad1[0x03c - 0x034 - 4]; 162 u32 aib; /*0x03c*/ 163 u32 sw_jtag; /*0x040*/ 164 u32 timer1; /*0x044*/ 165 u32 onewire; /*0x048*/ 166 u8 pad2[0x050 - 0x048 - 4]; 167 u32 asfar; /*0x050 AIB Secure First Access Reg*/ 168 u32 assar; /*0x054 AIB Secure Second Access Reg*/ 169 u8 pad3[0x06c - 0x054 - 4]; 170 u32 twsi1; /*0x06c*/ 171 u32 uart3; /*0x070*/ 172 u8 pad4[0x07c - 0x070 - 4]; 173 u32 timer2; /*0x07C*/ 174 u8 pad5[0x084 - 0x07c - 4]; 175 u32 ac97; /*0x084*/ 176 }; 177 178 #endif /* CONFIG_ARMADA100 */ 179 #endif /* _ASM_ARCH_ARMADA100_H */ 180