18a8f084eSChandan Nath /* 28a8f084eSChandan Nath * omap.h 38a8f084eSChandan Nath * 48a8f084eSChandan Nath * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 58a8f084eSChandan Nath * 68a8f084eSChandan Nath * Author: 78a8f084eSChandan Nath * Chandan Nath <chandan.nath@ti.com> 88a8f084eSChandan Nath * 98a8f084eSChandan Nath * Derived from OMAP4 work by 108a8f084eSChandan Nath * Aneesh V <aneesh@ti.com> 118a8f084eSChandan Nath * 128a8f084eSChandan Nath * This program is free software; you can redistribute it and/or 138a8f084eSChandan Nath * modify it under the terms of the GNU General Public License as 148a8f084eSChandan Nath * published by the Free Software Foundation; either version 2 of 158a8f084eSChandan Nath * the License, or (at your option) any later version. 168a8f084eSChandan Nath * 178a8f084eSChandan Nath * This program is distributed in the hope that it will be useful, 188a8f084eSChandan Nath * but WITHOUT ANY WARRANTY; without even the implied warranty of 198a8f084eSChandan Nath * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 208a8f084eSChandan Nath * GNU General Public License for more details. 218a8f084eSChandan Nath */ 228a8f084eSChandan Nath 238a8f084eSChandan Nath #ifndef _OMAP_H_ 248a8f084eSChandan Nath #define _OMAP_H_ 258a8f084eSChandan Nath 268a8f084eSChandan Nath /* 278a8f084eSChandan Nath * Non-secure SRAM Addresses 288a8f084eSChandan Nath * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE 298a8f084eSChandan Nath * at 0x40304000(EMU base) so that our code works for both EMU and GP 308a8f084eSChandan Nath */ 31*8b029f22SMatt Porter #ifdef CONFIG_AM33XX 328a8f084eSChandan Nath #define NON_SECURE_SRAM_START 0x40304000 338a8f084eSChandan Nath #define NON_SECURE_SRAM_END 0x4030E000 34*8b029f22SMatt Porter #elif defined(CONFIG_TI814X) 35*8b029f22SMatt Porter #define NON_SECURE_SRAM_START 0x40300000 36*8b029f22SMatt Porter #define NON_SECURE_SRAM_END 0x40320000 37*8b029f22SMatt Porter #endif 388a8f084eSChandan Nath 398a8f084eSChandan Nath /* ROM code defines */ 408a8f084eSChandan Nath /* Boot device */ 418a8f084eSChandan Nath #define BOOT_DEVICE_MASK 0xFF 428a8f084eSChandan Nath #define BOOT_DEVICE_OFFSET 0x8 438a8f084eSChandan Nath #define DEV_DESC_PTR_OFFSET 0x4 448a8f084eSChandan Nath #define DEV_DATA_PTR_OFFSET 0x18 458a8f084eSChandan Nath #define BOOT_MODE_OFFSET 0x8 468a8f084eSChandan Nath #define RESET_REASON_OFFSET 0x9 478a8f084eSChandan Nath #define CH_FLAGS_OFFSET 0xA 488a8f084eSChandan Nath 498a8f084eSChandan Nath #define CH_FLAGS_CHSETTINGS (0x1 << 0) 508a8f084eSChandan Nath #define CH_FLAGS_CHRAM (0x1 << 1) 518a8f084eSChandan Nath #define CH_FLAGS_CHFLASH (0x1 << 2) 528a8f084eSChandan Nath #define CH_FLAGS_CHMMCSD (0x1 << 3) 538a8f084eSChandan Nath 548a8f084eSChandan Nath #ifndef __ASSEMBLY__ 558a8f084eSChandan Nath struct omap_boot_parameters { 568a8f084eSChandan Nath char *boot_message; 578a8f084eSChandan Nath unsigned int mem_boot_descriptor; 588a8f084eSChandan Nath unsigned char omap_bootdevice; 598a8f084eSChandan Nath unsigned char reset_reason; 608a8f084eSChandan Nath unsigned char ch_flags; 618a8f084eSChandan Nath }; 628a8f084eSChandan Nath #endif 638a8f084eSChandan Nath #endif 64