1*8a8f084eSChandan Nath /* 2*8a8f084eSChandan Nath * omap.h 3*8a8f084eSChandan Nath * 4*8a8f084eSChandan Nath * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 5*8a8f084eSChandan Nath * 6*8a8f084eSChandan Nath * Author: 7*8a8f084eSChandan Nath * Chandan Nath <chandan.nath@ti.com> 8*8a8f084eSChandan Nath * 9*8a8f084eSChandan Nath * Derived from OMAP4 work by 10*8a8f084eSChandan Nath * Aneesh V <aneesh@ti.com> 11*8a8f084eSChandan Nath * 12*8a8f084eSChandan Nath * This program is free software; you can redistribute it and/or 13*8a8f084eSChandan Nath * modify it under the terms of the GNU General Public License as 14*8a8f084eSChandan Nath * published by the Free Software Foundation; either version 2 of 15*8a8f084eSChandan Nath * the License, or (at your option) any later version. 16*8a8f084eSChandan Nath * 17*8a8f084eSChandan Nath * This program is distributed in the hope that it will be useful, 18*8a8f084eSChandan Nath * but WITHOUT ANY WARRANTY; without even the implied warranty of 19*8a8f084eSChandan Nath * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 20*8a8f084eSChandan Nath * GNU General Public License for more details. 21*8a8f084eSChandan Nath */ 22*8a8f084eSChandan Nath 23*8a8f084eSChandan Nath #ifndef _OMAP_H_ 24*8a8f084eSChandan Nath #define _OMAP_H_ 25*8a8f084eSChandan Nath 26*8a8f084eSChandan Nath /* 27*8a8f084eSChandan Nath * Non-secure SRAM Addresses 28*8a8f084eSChandan Nath * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE 29*8a8f084eSChandan Nath * at 0x40304000(EMU base) so that our code works for both EMU and GP 30*8a8f084eSChandan Nath */ 31*8a8f084eSChandan Nath #define NON_SECURE_SRAM_START 0x40304000 32*8a8f084eSChandan Nath #define NON_SECURE_SRAM_END 0x4030E000 33*8a8f084eSChandan Nath #define LOW_LEVEL_SRAM_STACK 0x4030B7FC 34*8a8f084eSChandan Nath 35*8a8f084eSChandan Nath /* ROM code defines */ 36*8a8f084eSChandan Nath /* Boot device */ 37*8a8f084eSChandan Nath #define BOOT_DEVICE_MASK 0xFF 38*8a8f084eSChandan Nath #define BOOT_DEVICE_OFFSET 0x8 39*8a8f084eSChandan Nath #define DEV_DESC_PTR_OFFSET 0x4 40*8a8f084eSChandan Nath #define DEV_DATA_PTR_OFFSET 0x18 41*8a8f084eSChandan Nath #define BOOT_MODE_OFFSET 0x8 42*8a8f084eSChandan Nath #define RESET_REASON_OFFSET 0x9 43*8a8f084eSChandan Nath #define CH_FLAGS_OFFSET 0xA 44*8a8f084eSChandan Nath 45*8a8f084eSChandan Nath #define CH_FLAGS_CHSETTINGS (0x1 << 0) 46*8a8f084eSChandan Nath #define CH_FLAGS_CHRAM (0x1 << 1) 47*8a8f084eSChandan Nath #define CH_FLAGS_CHFLASH (0x1 << 2) 48*8a8f084eSChandan Nath #define CH_FLAGS_CHMMCSD (0x1 << 3) 49*8a8f084eSChandan Nath 50*8a8f084eSChandan Nath #ifndef __ASSEMBLY__ 51*8a8f084eSChandan Nath struct omap_boot_parameters { 52*8a8f084eSChandan Nath char *boot_message; 53*8a8f084eSChandan Nath unsigned int mem_boot_descriptor; 54*8a8f084eSChandan Nath unsigned char omap_bootdevice; 55*8a8f084eSChandan Nath unsigned char reset_reason; 56*8a8f084eSChandan Nath unsigned char ch_flags; 57*8a8f084eSChandan Nath }; 58*8a8f084eSChandan Nath #endif 59*8a8f084eSChandan Nath #endif 60