18a8f084eSChandan Nath /* 28a8f084eSChandan Nath * omap.h 38a8f084eSChandan Nath * 48a8f084eSChandan Nath * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 58a8f084eSChandan Nath * 68a8f084eSChandan Nath * Author: 78a8f084eSChandan Nath * Chandan Nath <chandan.nath@ti.com> 88a8f084eSChandan Nath * 98a8f084eSChandan Nath * Derived from OMAP4 work by 108a8f084eSChandan Nath * Aneesh V <aneesh@ti.com> 118a8f084eSChandan Nath * 12*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 138a8f084eSChandan Nath */ 148a8f084eSChandan Nath 158a8f084eSChandan Nath #ifndef _OMAP_H_ 168a8f084eSChandan Nath #define _OMAP_H_ 178a8f084eSChandan Nath 188a8f084eSChandan Nath /* 198a8f084eSChandan Nath * Non-secure SRAM Addresses 208a8f084eSChandan Nath * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE 218a8f084eSChandan Nath * at 0x40304000(EMU base) so that our code works for both EMU and GP 228a8f084eSChandan Nath */ 238b029f22SMatt Porter #ifdef CONFIG_AM33XX 24320d9746STom Rini #define NON_SECURE_SRAM_START 0x402F0400 25320d9746STom Rini #define NON_SECURE_SRAM_END 0x40310000 26edfcf85aSTom Rini #define SRAM_SCRATCH_SPACE_ADDR 0x4030C000 278b029f22SMatt Porter #elif defined(CONFIG_TI814X) 288b029f22SMatt Porter #define NON_SECURE_SRAM_START 0x40300000 298b029f22SMatt Porter #define NON_SECURE_SRAM_END 0x40320000 30edfcf85aSTom Rini #define SRAM_SCRATCH_SPACE_ADDR 0x4031B800 318b029f22SMatt Porter #endif 328a8f084eSChandan Nath #endif 33