1 /*
2  * mmc_host_def.h
3  *
4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 
16 #ifndef MMC_HOST_DEF_H
17 #define MMC_HOST_DEF_H
18 
19 /*
20  * OMAP HSMMC register definitions
21  */
22 #define OMAP_HSMMC1_BASE		0x48060100
23 #define OMAP_HSMMC2_BASE		0x481D8000
24 #define OMAP_HSMMC3_BASE		0x47C24000
25 
26 typedef struct hsmmc {
27 	unsigned char res1[0x10];
28 	unsigned int sysconfig;		/* 0x10 */
29 	unsigned int sysstatus;		/* 0x14 */
30 	unsigned char res2[0x14];
31 	unsigned int con;		/* 0x2C */
32 	unsigned char res3[0xD4];
33 	unsigned int blk;		/* 0x104 */
34 	unsigned int arg;		/* 0x108 */
35 	unsigned int cmd;		/* 0x10C */
36 	unsigned int rsp10;		/* 0x110 */
37 	unsigned int rsp32;		/* 0x114 */
38 	unsigned int rsp54;		/* 0x118 */
39 	unsigned int rsp76;		/* 0x11C */
40 	unsigned int data;		/* 0x120 */
41 	unsigned int pstate;		/* 0x124 */
42 	unsigned int hctl;		/* 0x128 */
43 	unsigned int sysctl;		/* 0x12C */
44 	unsigned int stat;		/* 0x130 */
45 	unsigned int ie;		/* 0x134 */
46 	unsigned char res4[0x8];
47 	unsigned int capa;		/* 0x140 */
48 } hsmmc_t;
49 
50 /*
51  * OMAP HS MMC Bit definitions
52  */
53 #define MMC_SOFTRESET			(0x1 << 1)
54 #define RESETDONE			(0x1 << 0)
55 #define NOOPENDRAIN			(0x0 << 0)
56 #define OPENDRAIN			(0x1 << 0)
57 #define OD				(0x1 << 0)
58 #define INIT_NOINIT			(0x0 << 1)
59 #define INIT_INITSTREAM			(0x1 << 1)
60 #define HR_NOHOSTRESP			(0x0 << 2)
61 #define STR_BLOCK			(0x0 << 3)
62 #define MODE_FUNC			(0x0 << 4)
63 #define DW8_1_4BITMODE			(0x0 << 5)
64 #define MIT_CTO				(0x0 << 6)
65 #define CDP_ACTIVEHIGH			(0x0 << 7)
66 #define WPP_ACTIVEHIGH			(0x0 << 8)
67 #define RESERVED_MASK			(0x3 << 9)
68 #define CTPL_MMC_SD			(0x0 << 11)
69 #define BLEN_512BYTESLEN		(0x200 << 0)
70 #define NBLK_STPCNT			(0x0 << 16)
71 #define DE_DISABLE			(0x0 << 0)
72 #define BCE_DISABLE			(0x0 << 1)
73 #define BCE_ENABLE			(0x1 << 1)
74 #define ACEN_DISABLE			(0x0 << 2)
75 #define DDIR_OFFSET			(4)
76 #define DDIR_MASK			(0x1 << 4)
77 #define DDIR_WRITE			(0x0 << 4)
78 #define DDIR_READ			(0x1 << 4)
79 #define MSBS_SGLEBLK			(0x0 << 5)
80 #define MSBS_MULTIBLK			(0x1 << 5)
81 #define RSP_TYPE_OFFSET			(16)
82 #define RSP_TYPE_MASK			(0x3 << 16)
83 #define RSP_TYPE_NORSP			(0x0 << 16)
84 #define RSP_TYPE_LGHT136		(0x1 << 16)
85 #define RSP_TYPE_LGHT48			(0x2 << 16)
86 #define RSP_TYPE_LGHT48B		(0x3 << 16)
87 #define CCCE_NOCHECK			(0x0 << 19)
88 #define CCCE_CHECK			(0x1 << 19)
89 #define CICE_NOCHECK			(0x0 << 20)
90 #define CICE_CHECK			(0x1 << 20)
91 #define DP_OFFSET			(21)
92 #define DP_MASK				(0x1 << 21)
93 #define DP_NO_DATA			(0x0 << 21)
94 #define DP_DATA				(0x1 << 21)
95 #define CMD_TYPE_NORMAL			(0x0 << 22)
96 #define INDEX_OFFSET			(24)
97 #define INDEX_MASK			(0x3f << 24)
98 #define INDEX(i)			(i << 24)
99 #define DATI_MASK			(0x1 << 1)
100 #define CMDI_MASK			(0x1 << 0)
101 #define DTW_1_BITMODE			(0x0 << 1)
102 #define DTW_4_BITMODE			(0x1 << 1)
103 #define DTW_8_BITMODE                   (0x1 << 5) /* CON[DW8]*/
104 #define SDBP_PWROFF			(0x0 << 8)
105 #define SDBP_PWRON			(0x1 << 8)
106 #define SDVS_1V8			(0x5 << 9)
107 #define SDVS_3V0			(0x6 << 9)
108 #define ICE_MASK			(0x1 << 0)
109 #define ICE_STOP			(0x0 << 0)
110 #define ICS_MASK			(0x1 << 1)
111 #define ICS_NOTREADY			(0x0 << 1)
112 #define ICE_OSCILLATE			(0x1 << 0)
113 #define CEN_MASK			(0x1 << 2)
114 #define CEN_DISABLE			(0x0 << 2)
115 #define CEN_ENABLE			(0x1 << 2)
116 #define CLKD_OFFSET			(6)
117 #define CLKD_MASK			(0x3FF << 6)
118 #define DTO_MASK			(0xF << 16)
119 #define DTO_15THDTO			(0xE << 16)
120 #define SOFTRESETALL			(0x1 << 24)
121 #define CC_MASK				(0x1 << 0)
122 #define TC_MASK				(0x1 << 1)
123 #define BWR_MASK			(0x1 << 4)
124 #define BRR_MASK			(0x1 << 5)
125 #define ERRI_MASK			(0x1 << 15)
126 #define IE_CC				(0x01 << 0)
127 #define IE_TC				(0x01 << 1)
128 #define IE_BWR				(0x01 << 4)
129 #define IE_BRR				(0x01 << 5)
130 #define IE_CTO				(0x01 << 16)
131 #define IE_CCRC				(0x01 << 17)
132 #define IE_CEB				(0x01 << 18)
133 #define IE_CIE				(0x01 << 19)
134 #define IE_DTO				(0x01 << 20)
135 #define IE_DCRC				(0x01 << 21)
136 #define IE_DEB				(0x01 << 22)
137 #define IE_CERR				(0x01 << 28)
138 #define IE_BADA				(0x01 << 29)
139 
140 #define VS30_3V0SUP			(1 << 25)
141 #define VS18_1V8SUP			(1 << 26)
142 
143 /* Driver definitions */
144 #define MMCSD_SECTOR_SIZE		512
145 #define MMC_CARD			0
146 #define SD_CARD				1
147 #define BYTE_MODE			0
148 #define SECTOR_MODE			1
149 #define CLK_INITSEQ			0
150 #define CLK_400KHZ			1
151 #define CLK_MISC			2
152 
153 #define RSP_TYPE_NONE	(RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
154 #define MMC_CMD0	(INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
155 
156 /* Clock Configurations and Macros */
157 #define MMC_CLOCK_REFERENCE	96 /* MHz */
158 
159 #define mmc_reg_out(addr, mask, val)\
160 	writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
161 
162 int omap_mmc_init(int dev_index);
163 
164 #endif /* MMC_HOST_DEF_H */
165