1 /*
2  * (C) Copyright 2006-2008
3  * Texas Instruments, <www.ti.com>
4  *
5  * Author
6  *		Mansoor Ahamed <mansoor.ahamed@ti.com>
7  *
8  * Initial Code from:
9  *		Richard Woodruff <r-woodruff2@ti.com>
10  *
11  * See file CREDITS for list of people who contributed to this
12  * project.
13  *
14  * This program is free software; you can redistribute it and/or
15  * modify it under the terms of the GNU General Public License as
16  * published by the Free Software Foundation; either version 2 of
17  * the License, or (at your option) any later version.
18  *
19  * This program is distributed in the hope that it will be useful,
20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22  * GNU General Public License for more details.
23  *
24  * You should have received a copy of the GNU General Public License
25  * along with this program; if not, write to the Free Software
26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27  * MA 02111-1307 USA
28  */
29 
30 #ifndef _MEM_H_
31 #define _MEM_H_
32 
33 /*
34  * GPMC settings -
35  * Definitions is as per the following format
36  * #define <PART>_GPMC_CONFIG<x> <value>
37  * Where:
38  * PART is the part name e.g. STNOR - Intel Strata Flash
39  * x is GPMC config registers from 1 to 6 (there will be 6 macros)
40  * Value is corresponding value
41  *
42  * For every valid PRCM configuration there should be only one definition of
43  * the same. if values are independent of the board, this definition will be
44  * present in this file if values are dependent on the board, then this should
45  * go into corresponding mem-boardName.h file
46  *
47  * Currently valid part Names are (PART):
48  * M_NAND - Micron NAND
49  */
50 #define GPMC_SIZE_256M		0x0
51 #define GPMC_SIZE_128M		0x8
52 #define GPMC_SIZE_64M		0xC
53 #define GPMC_SIZE_32M		0xE
54 #define GPMC_SIZE_16M		0xF
55 
56 #define M_NAND_GPMC_CONFIG1	0x00000800
57 #define M_NAND_GPMC_CONFIG2	0x001e1e00
58 #define M_NAND_GPMC_CONFIG3	0x001e1e00
59 #define M_NAND_GPMC_CONFIG4	0x16051807
60 #define M_NAND_GPMC_CONFIG5	0x00151e1e
61 #define M_NAND_GPMC_CONFIG6	0x16000f80
62 #define M_NAND_GPMC_CONFIG7	0x00000008
63 
64 /* max number of GPMC Chip Selects */
65 #define GPMC_MAX_CS		8
66 /* max number of GPMC regs */
67 #define GPMC_MAX_REG		7
68 
69 #define PISMO1_NOR		1
70 #define PISMO1_NAND		2
71 #define PISMO2_CS0		3
72 #define PISMO2_CS1		4
73 #define PISMO1_ONENAND		5
74 #define DBG_MPDB		6
75 #define PISMO2_NAND_CS0		7
76 #define PISMO2_NAND_CS1		8
77 
78 /* make it readable for the gpmc_init */
79 #define PISMO1_NOR_BASE	FLASH_BASE
80 #define PISMO1_NAND_BASE	CONFIG_SYS_NAND_BASE
81 #define PISMO1_NAND_SIZE	GPMC_SIZE_256M
82 
83 #endif /* endif _MEM_H_ */
84