18eb16b7fSIlya Yanok /* 28eb16b7fSIlya Yanok * (C) Copyright 2006-2008 38eb16b7fSIlya Yanok * Texas Instruments, <www.ti.com> 48eb16b7fSIlya Yanok * 58eb16b7fSIlya Yanok * Author 68eb16b7fSIlya Yanok * Mansoor Ahamed <mansoor.ahamed@ti.com> 78eb16b7fSIlya Yanok * 88eb16b7fSIlya Yanok * Initial Code from: 98eb16b7fSIlya Yanok * Richard Woodruff <r-woodruff2@ti.com> 108eb16b7fSIlya Yanok * 111a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 128eb16b7fSIlya Yanok */ 138eb16b7fSIlya Yanok 148eb16b7fSIlya Yanok #ifndef _MEM_H_ 158eb16b7fSIlya Yanok #define _MEM_H_ 168eb16b7fSIlya Yanok 178eb16b7fSIlya Yanok /* 188eb16b7fSIlya Yanok * GPMC settings - 198eb16b7fSIlya Yanok * Definitions is as per the following format 208eb16b7fSIlya Yanok * #define <PART>_GPMC_CONFIG<x> <value> 218eb16b7fSIlya Yanok * Where: 228eb16b7fSIlya Yanok * PART is the part name e.g. STNOR - Intel Strata Flash 238eb16b7fSIlya Yanok * x is GPMC config registers from 1 to 6 (there will be 6 macros) 248eb16b7fSIlya Yanok * Value is corresponding value 258eb16b7fSIlya Yanok * 268eb16b7fSIlya Yanok * For every valid PRCM configuration there should be only one definition of 278eb16b7fSIlya Yanok * the same. if values are independent of the board, this definition will be 288eb16b7fSIlya Yanok * present in this file if values are dependent on the board, then this should 298eb16b7fSIlya Yanok * go into corresponding mem-boardName.h file 308eb16b7fSIlya Yanok * 318eb16b7fSIlya Yanok * Currently valid part Names are (PART): 328eb16b7fSIlya Yanok * M_NAND - Micron NAND 33*cd8845d7SSteve Kipisz * STNOR - STMicrolelctronics M29W128GL 348eb16b7fSIlya Yanok */ 358eb16b7fSIlya Yanok #define GPMC_SIZE_256M 0x0 368eb16b7fSIlya Yanok #define GPMC_SIZE_128M 0x8 378eb16b7fSIlya Yanok #define GPMC_SIZE_64M 0xC 388eb16b7fSIlya Yanok #define GPMC_SIZE_32M 0xE 398eb16b7fSIlya Yanok #define GPMC_SIZE_16M 0xF 408eb16b7fSIlya Yanok 418eb16b7fSIlya Yanok #define M_NAND_GPMC_CONFIG1 0x00000800 428eb16b7fSIlya Yanok #define M_NAND_GPMC_CONFIG2 0x001e1e00 438eb16b7fSIlya Yanok #define M_NAND_GPMC_CONFIG3 0x001e1e00 448eb16b7fSIlya Yanok #define M_NAND_GPMC_CONFIG4 0x16051807 458eb16b7fSIlya Yanok #define M_NAND_GPMC_CONFIG5 0x00151e1e 468eb16b7fSIlya Yanok #define M_NAND_GPMC_CONFIG6 0x16000f80 478eb16b7fSIlya Yanok #define M_NAND_GPMC_CONFIG7 0x00000008 488eb16b7fSIlya Yanok 49*cd8845d7SSteve Kipisz #define STNOR_GPMC_CONFIG1 0x00001200 50*cd8845d7SSteve Kipisz #define STNOR_GPMC_CONFIG2 0x00101000 51*cd8845d7SSteve Kipisz #define STNOR_GPMC_CONFIG3 0x00030301 52*cd8845d7SSteve Kipisz #define STNOR_GPMC_CONFIG4 0x10041004 53*cd8845d7SSteve Kipisz #define STNOR_GPMC_CONFIG5 0x000C1010 54*cd8845d7SSteve Kipisz #define STNOR_GPMC_CONFIG6 0x08070280 55*cd8845d7SSteve Kipisz #define STNOR_GPMC_CONFIG7 0x00000F48 56*cd8845d7SSteve Kipisz 578eb16b7fSIlya Yanok /* max number of GPMC Chip Selects */ 588eb16b7fSIlya Yanok #define GPMC_MAX_CS 8 598eb16b7fSIlya Yanok /* max number of GPMC regs */ 608eb16b7fSIlya Yanok #define GPMC_MAX_REG 7 618eb16b7fSIlya Yanok 628eb16b7fSIlya Yanok #define PISMO1_NOR 1 638eb16b7fSIlya Yanok #define PISMO1_NAND 2 648eb16b7fSIlya Yanok #define PISMO2_CS0 3 658eb16b7fSIlya Yanok #define PISMO2_CS1 4 668eb16b7fSIlya Yanok #define PISMO1_ONENAND 5 678eb16b7fSIlya Yanok #define DBG_MPDB 6 688eb16b7fSIlya Yanok #define PISMO2_NAND_CS0 7 698eb16b7fSIlya Yanok #define PISMO2_NAND_CS1 8 708eb16b7fSIlya Yanok 718eb16b7fSIlya Yanok /* make it readable for the gpmc_init */ 728eb16b7fSIlya Yanok #define PISMO1_NOR_BASE FLASH_BASE 738eb16b7fSIlya Yanok #define PISMO1_NAND_BASE CONFIG_SYS_NAND_BASE 748eb16b7fSIlya Yanok #define PISMO1_NAND_SIZE GPMC_SIZE_256M 758eb16b7fSIlya Yanok 768eb16b7fSIlya Yanok #endif /* endif _MEM_H_ */ 77