1 /* 2 * hardware_ti814x.h 3 * 4 * TI814x hardware specific header 5 * 6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __AM33XX_HARDWARE_TI814X_H 12 #define __AM33XX_HARDWARE_TI814X_H 13 14 /* Module base addresses */ 15 16 /* UART Base Address */ 17 #define UART0_BASE 0x48020000 18 19 /* Watchdog Timer */ 20 #define WDT_BASE 0x481C7000 21 22 /* Control Module Base Address */ 23 #define CTRL_BASE 0x48140000 24 #define CTRL_DEVICE_BASE 0x48140600 25 26 /* PRCM Base Address */ 27 #define PRCM_BASE 0x48180000 28 #define CM_PER 0x44E00000 29 #define CM_WKUP 0x44E00400 30 31 #define PRM_RSTCTRL (PRCM_BASE + 0x00A0) 32 #define PRM_RSTST (PRM_RSTCTRL + 8) 33 34 /* PLL Subsystem Base Address */ 35 #define PLL_SUBSYS_BASE 0x481C5000 36 37 /* VTP Base address */ 38 #define VTP0_CTRL_ADDR 0x48140E0C 39 #define VTP1_CTRL_ADDR 0x48140E10 40 41 /* DDR Base address */ 42 #define DDR_PHY_CMD_ADDR 0x47C0C400 43 #define DDR_PHY_DATA_ADDR 0x47C0C4C8 44 #define DDR_PHY_CMD_ADDR2 0x47C0C800 45 #define DDR_PHY_DATA_ADDR2 0x47C0C8C8 46 #define DDR_DATA_REGS_NR 4 47 48 #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) 49 #define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE 50 51 /* CPSW Config space */ 52 #define CPSW_MDIO_BASE 0x4A100800 53 54 /* RTC base address */ 55 #define RTC_BASE 0x480C0000 56 57 /* OTG */ 58 #define USB0_OTG_BASE 0x47401000 59 #define USB1_OTG_BASE 0x47401800 60 61 #endif /* __AM33XX_HARDWARE_TI814X_H */ 62