1 /* 2 * hardware_am43xx.h 3 * 4 * AM43xx hardware specific header 5 * 6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __AM43XX_HARDWARE_AM43XX_H 12 #define __AM43XX_HARDWARE_AM43XX_H 13 14 /* Module base addresses */ 15 16 /* L3 Fast Configuration Bandwidth Limiter Base Address */ 17 #define L3F_CFG_BWLIMITER 0x44005200 18 19 /* UART Base Address */ 20 #define UART0_BASE 0x44E09000 21 22 /* GPIO Base address */ 23 #define GPIO2_BASE 0x481AC000 24 25 /* Watchdog Timer */ 26 #define WDT_BASE 0x44E35000 27 28 /* Control Module Base Address */ 29 #define CTRL_BASE 0x44E10000 30 #define CTRL_DEVICE_BASE 0x44E10600 31 32 /* PRCM Base Address */ 33 #define PRCM_BASE 0x44DF0000 34 #define CM_WKUP 0x44DF2800 35 #define CM_PER 0x44DF8800 36 #define CM_DPLL 0x44DF4200 37 #define CM_RTC 0x44DF8500 38 39 #define PRM_RSTCTRL (PRCM_BASE + 0x4000) 40 #define PRM_RSTST (PRM_RSTCTRL + 4) 41 42 /* VTP Base address */ 43 #define VTP0_CTRL_ADDR 0x44E10E0C 44 #define VTP1_CTRL_ADDR 0x48140E10 45 46 /* DDR Base address */ 47 #define DDR_PHY_CMD_ADDR 0x44E12000 48 #define DDR_PHY_DATA_ADDR 0x44E120C8 49 #define DDR_PHY_CMD_ADDR2 0x47C0C800 50 #define DDR_PHY_DATA_ADDR2 0x47C0C8C8 51 #define DDR_DATA_REGS_NR 2 52 53 /* CPSW Config space */ 54 #define CPSW_MDIO_BASE 0x4A101000 55 56 /* RTC base address */ 57 #define RTC_BASE 0x44E3E000 58 59 /* USB Clock Control */ 60 #define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260) 61 #define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268) 62 #define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1) 63 #define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) 64 65 #define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8) 66 #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) 67 #define USBPHYOCPSCP_MODULE_EN (1 << 1) 68 #define CM_DEVICE_INST 0x44df4100 69 70 /* Control status register */ 71 #define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) 72 #define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31 73 #define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29) 74 #define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29 75 #define CTRL_SYSBOOT_15_14_MASK (0x3 << 22) 76 #define CTRL_SYSBOOT_15_14_SHIFT 22 77 78 #define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0 79 #define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1 80 81 #define NUM_CRYSTAL_FREQ 0x4 82 83 #endif /* __AM43XX_HARDWARE_AM43XX_H */ 84