1 /* 2 * hardware_am43xx.h 3 * 4 * AM43xx hardware specific header 5 * 6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __AM43XX_HARDWARE_AM43XX_H 12 #define __AM43XX_HARDWARE_AM43XX_H 13 14 /* Module base addresses */ 15 16 /* UART Base Address */ 17 #define UART0_BASE 0x44E09000 18 19 /* GPIO Base address */ 20 #define GPIO2_BASE 0x481AC000 21 22 /* Watchdog Timer */ 23 #define WDT_BASE 0x44E35000 24 25 /* Control Module Base Address */ 26 #define CTRL_BASE 0x44E10000 27 #define CTRL_DEVICE_BASE 0x44E10600 28 29 /* PRCM Base Address */ 30 #define PRCM_BASE 0x44DF0000 31 #define CM_WKUP 0x44DF2800 32 #define CM_PER 0x44DF8800 33 #define CM_DPLL 0x44DF4200 34 #define CM_RTC 0x44DF8500 35 36 #define PRM_RSTCTRL (PRCM_BASE + 0x4000) 37 #define PRM_RSTST (PRM_RSTCTRL + 4) 38 39 /* VTP Base address */ 40 #define VTP0_CTRL_ADDR 0x44E10E0C 41 #define VTP1_CTRL_ADDR 0x48140E10 42 43 /* DDR Base address */ 44 #define DDR_PHY_CMD_ADDR 0x44E12000 45 #define DDR_PHY_DATA_ADDR 0x44E120C8 46 #define DDR_PHY_CMD_ADDR2 0x47C0C800 47 #define DDR_PHY_DATA_ADDR2 0x47C0C8C8 48 #define DDR_DATA_REGS_NR 2 49 50 /* CPSW Config space */ 51 #define CPSW_MDIO_BASE 0x4A101000 52 53 /* RTC base address */ 54 #define RTC_BASE 0x44E3E000 55 56 /* USB Clock Control */ 57 #define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260) 58 #define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268) 59 #define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1) 60 #define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) 61 62 #define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8) 63 #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) 64 #define USBPHYOCPSCP_MODULE_EN (1 << 1) 65 #define CM_DEVICE_INST 0x44df4100 66 67 /* Control status register */ 68 #define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) 69 #define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31 70 #define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29) 71 #define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29 72 #define CTRL_SYSBOOT_15_14_MASK (0x3 << 22) 73 #define CTRL_SYSBOOT_15_14_SHIFT 22 74 75 #define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0 76 #define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1 77 78 #define NUM_CRYSTAL_FREQ 0x4 79 80 #endif /* __AM43XX_HARDWARE_AM43XX_H */ 81