1 /*
2  * hardware_am33xx.h
3  *
4  * AM33xx hardware specific header
5  *
6  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #ifndef __AM33XX_HARDWARE_AM33XX_H
12 #define __AM33XX_HARDWARE_AM33XX_H
13 
14 /* Module base addresses */
15 
16 /* UART Base Address */
17 #define UART0_BASE			0x44E09000
18 
19 /* GPIO Base address */
20 #define GPIO2_BASE			0x481AC000
21 
22 /* Watchdog Timer */
23 #define WDT_BASE			0x44E35000
24 
25 /* Control Module Base Address */
26 #define CTRL_BASE			0x44E10000
27 #define CTRL_DEVICE_BASE		0x44E10600
28 
29 /* PRCM Base Address */
30 #define PRCM_BASE			0x44E00000
31 #define CM_PER				0x44E00000
32 #define CM_WKUP				0x44E00400
33 
34 #define PRM_RSTCTRL			(PRCM_BASE + 0x0F00)
35 #define PRM_RSTST			(PRM_RSTCTRL + 8)
36 
37 /* VTP Base address */
38 #define VTP0_CTRL_ADDR			0x44E10E0C
39 #define VTP1_CTRL_ADDR			0x48140E10
40 
41 /* DDR Base address */
42 #define DDR_PHY_CMD_ADDR		0x44E12000
43 #define DDR_PHY_DATA_ADDR		0x44E120C8
44 #define DDR_PHY_CMD_ADDR2		0x47C0C800
45 #define DDR_PHY_DATA_ADDR2		0x47C0C8C8
46 #define DDR_DATA_REGS_NR		2
47 
48 #define DDRPHY_0_CONFIG_BASE		(CTRL_BASE + 0x1400)
49 #define DDRPHY_CONFIG_BASE		DDRPHY_0_CONFIG_BASE
50 
51 /* CPSW Config space */
52 #define CPSW_MDIO_BASE			0x4A101000
53 
54 /* RTC base address */
55 #define RTC_BASE			0x44E3E000
56 
57 /* OTG */
58 #define USB0_OTG_BASE			0x47401000
59 #define USB1_OTG_BASE			0x47401800
60 
61 /* LCD Controller */
62 #define LCD_CNTL_BASE			0x4830E000
63 
64 /* PWMSS */
65 #define PWMSS0_BASE			0x48300000
66 #define AM33XX_ECAP0_BASE		0x48300100
67 
68 #endif /* __AM33XX_HARDWARE_AM33XX_H */
69