1 /* 2 * ddr_defs.h 3 * 4 * ddr specific header 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _DDR_DEFS_H 12 #define _DDR_DEFS_H 13 14 #include <asm/arch/hardware.h> 15 #include <asm/emif.h> 16 17 /* AM335X EMIF Register values */ 18 #define VTP_CTRL_READY (0x1 << 5) 19 #define VTP_CTRL_ENABLE (0x1 << 6) 20 #define VTP_CTRL_START_EN (0x1) 21 #ifdef CONFIG_AM43XX 22 #define DDR_CKE_CTRL_NORMAL 0x3 23 #else 24 #define DDR_CKE_CTRL_NORMAL 0x1 25 #endif 26 #define PHY_EN_DYN_PWRDN (0x1 << 20) 27 28 /* Micron MT47H128M16RT-25E */ 29 #define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005 30 #define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9 31 #define MT47H128M16RT25E_EMIF_TIM2 0x243631CA 32 #define MT47H128M16RT25E_EMIF_TIM3 0x0000033F 33 #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 34 #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a 35 #define MT47H128M16RT25E_RATIO 0x80 36 #define MT47H128M16RT25E_INVERT_CLKOUT 0x00 37 #define MT47H128M16RT25E_RD_DQS 0x12 38 #define MT47H128M16RT25E_WR_DQS 0x00 39 #define MT47H128M16RT25E_PHY_WRLVL 0x00 40 #define MT47H128M16RT25E_PHY_GATELVL 0x00 41 #define MT47H128M16RT25E_PHY_WR_DATA 0x40 42 #define MT47H128M16RT25E_PHY_FIFO_WE 0x80 43 #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B 44 45 /* Micron MT41J128M16JT-125 */ 46 #define MT41J128MJT125_EMIF_READ_LATENCY 0x100006 47 #define MT41J128MJT125_EMIF_TIM1 0x0888A39B 48 #define MT41J128MJT125_EMIF_TIM2 0x26337FDA 49 #define MT41J128MJT125_EMIF_TIM3 0x501F830F 50 #define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2 51 #define MT41J128MJT125_EMIF_SDREF 0x0000093B 52 #define MT41J128MJT125_ZQ_CFG 0x50074BE4 53 #define MT41J128MJT125_RATIO 0x40 54 #define MT41J128MJT125_INVERT_CLKOUT 0x1 55 #define MT41J128MJT125_RD_DQS 0x3B 56 #define MT41J128MJT125_WR_DQS 0x85 57 #define MT41J128MJT125_PHY_WR_DATA 0xC1 58 #define MT41J128MJT125_PHY_FIFO_WE 0x100 59 #define MT41J128MJT125_IOCTRL_VALUE 0x18B 60 61 /* Micron MT41K128M16JT-187E */ 62 #define MT41K128MJT187E_EMIF_READ_LATENCY 0x06 63 #define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB 64 #define MT41K128MJT187E_EMIF_TIM2 0x36337FDA 65 #define MT41K128MJT187E_EMIF_TIM3 0x501F830F 66 #define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2 67 #define MT41K128MJT187E_EMIF_SDREF 0x0000093B 68 #define MT41K128MJT187E_ZQ_CFG 0x50074BE4 69 #define MT41K128MJT187E_RATIO 0x40 70 #define MT41K128MJT187E_INVERT_CLKOUT 0x1 71 #define MT41K128MJT187E_RD_DQS 0x3B 72 #define MT41K128MJT187E_WR_DQS 0x85 73 #define MT41K128MJT187E_PHY_WR_DATA 0xC1 74 #define MT41K128MJT187E_PHY_FIFO_WE 0x100 75 #define MT41K128MJT187E_IOCTRL_VALUE 0x18B 76 77 /* Micron MT41J64M16JT-125 */ 78 #define MT41J64MJT125_EMIF_SDCFG 0x61C04A32 79 80 /* Micron MT41J256M16JT-125 */ 81 #define MT41J256MJT125_EMIF_SDCFG 0x61C04B32 82 83 /* Micron MT41J256M8HX-15E */ 84 #define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006 85 #define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B 86 #define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA 87 #define MT41J256M8HX15E_EMIF_TIM3 0x501F830F 88 #define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32 89 #define MT41J256M8HX15E_EMIF_SDREF 0x0000093B 90 #define MT41J256M8HX15E_ZQ_CFG 0x50074BE4 91 #define MT41J256M8HX15E_RATIO 0x40 92 #define MT41J256M8HX15E_INVERT_CLKOUT 0x1 93 #define MT41J256M8HX15E_RD_DQS 0x3B 94 #define MT41J256M8HX15E_WR_DQS 0x85 95 #define MT41J256M8HX15E_PHY_WR_DATA 0xC1 96 #define MT41J256M8HX15E_PHY_FIFO_WE 0x100 97 #define MT41J256M8HX15E_IOCTRL_VALUE 0x18B 98 99 /* Micron MT41K256M16HA-125E */ 100 #define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007 101 #define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB 102 #define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA 103 #define MT41K256M16HA125E_EMIF_TIM3 0x501F867F 104 #define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332 105 #define MT41K256M16HA125E_EMIF_SDREF 0xC30 106 #define MT41K256M16HA125E_ZQ_CFG 0x50074BE4 107 #define MT41K256M16HA125E_RATIO 0x80 108 #define MT41K256M16HA125E_INVERT_CLKOUT 0x0 109 #define MT41K256M16HA125E_RD_DQS 0x38 110 #define MT41K256M16HA125E_WR_DQS 0x44 111 #define MT41K256M16HA125E_PHY_WR_DATA 0x7D 112 #define MT41K256M16HA125E_PHY_FIFO_WE 0x94 113 #define MT41K256M16HA125E_IOCTRL_VALUE 0x18B 114 115 /* Micron MT41J512M8RH-125 on EVM v1.5 */ 116 #define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006 117 #define MT41J512M8RH125_EMIF_TIM1 0x0888A39B 118 #define MT41J512M8RH125_EMIF_TIM2 0x26517FDA 119 #define MT41J512M8RH125_EMIF_TIM3 0x501F84EF 120 #define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2 121 #define MT41J512M8RH125_EMIF_SDREF 0x0000093B 122 #define MT41J512M8RH125_ZQ_CFG 0x50074BE4 123 #define MT41J512M8RH125_RATIO 0x80 124 #define MT41J512M8RH125_INVERT_CLKOUT 0x0 125 #define MT41J512M8RH125_RD_DQS 0x3B 126 #define MT41J512M8RH125_WR_DQS 0x3C 127 #define MT41J512M8RH125_PHY_FIFO_WE 0xA5 128 #define MT41J512M8RH125_PHY_WR_DATA 0x74 129 #define MT41J512M8RH125_IOCTRL_VALUE 0x18B 130 131 /* Samsung K4B2G1646E-BIH9 */ 132 #define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007 133 #define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B 134 #define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA 135 #define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF 136 #define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2 137 #define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30 138 #define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4 139 #define K4B2G1646EBIH9_RATIO 0x80 140 #define K4B2G1646EBIH9_INVERT_CLKOUT 0x0 141 #define K4B2G1646EBIH9_RD_DQS 0x35 142 #define K4B2G1646EBIH9_WR_DQS 0x3A 143 #define K4B2G1646EBIH9_PHY_FIFO_WE 0x97 144 #define K4B2G1646EBIH9_PHY_WR_DATA 0x76 145 #define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B 146 147 #define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294 148 #define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 149 #define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 150 #define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294 151 #define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294 152 #define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 153 #define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294 154 155 #define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 156 #define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 157 #define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84 158 #define DDR3_DATA0_IOCTRL_VALUE 0x84 159 #define DDR3_DATA1_IOCTRL_VALUE 0x84 160 #define DDR3_DATA2_IOCTRL_VALUE 0x84 161 #define DDR3_DATA3_IOCTRL_VALUE 0x84 162 163 /** 164 * Configure DMM 165 */ 166 void config_dmm(const struct dmm_lisa_map_regs *regs); 167 168 /** 169 * Configure SDRAM 170 */ 171 void config_sdram(const struct emif_regs *regs, int nr); 172 void config_sdram_emif4d5(const struct emif_regs *regs, int nr); 173 174 /** 175 * Set SDRAM timings 176 */ 177 void set_sdram_timings(const struct emif_regs *regs, int nr); 178 179 /** 180 * Configure DDR PHY 181 */ 182 void config_ddr_phy(const struct emif_regs *regs, int nr); 183 184 struct ddr_cmd_regs { 185 unsigned int resv0[7]; 186 unsigned int cm0csratio; /* offset 0x01C */ 187 unsigned int resv1[3]; 188 unsigned int cm0iclkout; /* offset 0x02C */ 189 unsigned int resv2[8]; 190 unsigned int cm1csratio; /* offset 0x050 */ 191 unsigned int resv3[3]; 192 unsigned int cm1iclkout; /* offset 0x060 */ 193 unsigned int resv4[8]; 194 unsigned int cm2csratio; /* offset 0x084 */ 195 unsigned int resv5[3]; 196 unsigned int cm2iclkout; /* offset 0x094 */ 197 unsigned int resv6[3]; 198 }; 199 200 struct ddr_data_regs { 201 unsigned int dt0rdsratio0; /* offset 0x0C8 */ 202 unsigned int resv1[4]; 203 unsigned int dt0wdsratio0; /* offset 0x0DC */ 204 unsigned int resv2[4]; 205 unsigned int dt0wiratio0; /* offset 0x0F0 */ 206 unsigned int resv3; 207 unsigned int dt0wimode0; /* offset 0x0F8 */ 208 unsigned int dt0giratio0; /* offset 0x0FC */ 209 unsigned int resv4; 210 unsigned int dt0gimode0; /* offset 0x104 */ 211 unsigned int dt0fwsratio0; /* offset 0x108 */ 212 unsigned int resv5[4]; 213 unsigned int dt0dqoffset; /* offset 0x11C */ 214 unsigned int dt0wrsratio0; /* offset 0x120 */ 215 unsigned int resv6[4]; 216 unsigned int dt0rdelays0; /* offset 0x134 */ 217 unsigned int dt0dldiff0; /* offset 0x138 */ 218 unsigned int resv7[12]; 219 }; 220 221 /** 222 * This structure represents the DDR registers on AM33XX devices. 223 * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that 224 * correspond to DATA1 registers defined here. 225 */ 226 struct ddr_regs { 227 unsigned int resv0[3]; 228 unsigned int cm0config; /* offset 0x00C */ 229 unsigned int cm0configclk; /* offset 0x010 */ 230 unsigned int resv1[2]; 231 unsigned int cm0csratio; /* offset 0x01C */ 232 unsigned int resv2[3]; 233 unsigned int cm0iclkout; /* offset 0x02C */ 234 unsigned int resv3[4]; 235 unsigned int cm1config; /* offset 0x040 */ 236 unsigned int cm1configclk; /* offset 0x044 */ 237 unsigned int resv4[2]; 238 unsigned int cm1csratio; /* offset 0x050 */ 239 unsigned int resv5[3]; 240 unsigned int cm1iclkout; /* offset 0x060 */ 241 unsigned int resv6[4]; 242 unsigned int cm2config; /* offset 0x074 */ 243 unsigned int cm2configclk; /* offset 0x078 */ 244 unsigned int resv7[2]; 245 unsigned int cm2csratio; /* offset 0x084 */ 246 unsigned int resv8[3]; 247 unsigned int cm2iclkout; /* offset 0x094 */ 248 unsigned int resv9[12]; 249 unsigned int dt0rdsratio0; /* offset 0x0C8 */ 250 unsigned int resv10[4]; 251 unsigned int dt0wdsratio0; /* offset 0x0DC */ 252 unsigned int resv11[4]; 253 unsigned int dt0wiratio0; /* offset 0x0F0 */ 254 unsigned int resv12; 255 unsigned int dt0wimode0; /* offset 0x0F8 */ 256 unsigned int dt0giratio0; /* offset 0x0FC */ 257 unsigned int resv13; 258 unsigned int dt0gimode0; /* offset 0x104 */ 259 unsigned int dt0fwsratio0; /* offset 0x108 */ 260 unsigned int resv14[4]; 261 unsigned int dt0dqoffset; /* offset 0x11C */ 262 unsigned int dt0wrsratio0; /* offset 0x120 */ 263 unsigned int resv15[4]; 264 unsigned int dt0rdelays0; /* offset 0x134 */ 265 unsigned int dt0dldiff0; /* offset 0x138 */ 266 }; 267 268 /** 269 * Encapsulates DDR CMD control registers. 270 */ 271 struct cmd_control { 272 unsigned long cmd0csratio; 273 unsigned long cmd0csforce; 274 unsigned long cmd0csdelay; 275 unsigned long cmd0iclkout; 276 unsigned long cmd1csratio; 277 unsigned long cmd1csforce; 278 unsigned long cmd1csdelay; 279 unsigned long cmd1iclkout; 280 unsigned long cmd2csratio; 281 unsigned long cmd2csforce; 282 unsigned long cmd2csdelay; 283 unsigned long cmd2iclkout; 284 }; 285 286 /** 287 * Encapsulates DDR DATA registers. 288 */ 289 struct ddr_data { 290 unsigned long datardsratio0; 291 unsigned long datawdsratio0; 292 unsigned long datawiratio0; 293 unsigned long datagiratio0; 294 unsigned long datafwsratio0; 295 unsigned long datawrsratio0; 296 }; 297 298 /** 299 * Configure DDR CMD control registers 300 */ 301 void config_cmd_ctrl(const struct cmd_control *cmd, int nr); 302 303 /** 304 * Configure DDR DATA registers 305 */ 306 void config_ddr_data(const struct ddr_data *data, int nr); 307 308 /** 309 * This structure represents the DDR io control on AM33XX devices. 310 */ 311 struct ddr_cmdtctrl { 312 unsigned int cm0ioctl; 313 unsigned int cm1ioctl; 314 unsigned int cm2ioctl; 315 unsigned int resv2[12]; 316 unsigned int dt0ioctl; 317 unsigned int dt1ioctl; 318 unsigned int dt2ioctrl; 319 unsigned int dt3ioctrl; 320 unsigned int resv3[4]; 321 unsigned int emif_sdram_config_ext; 322 }; 323 324 struct ctrl_ioregs { 325 unsigned int cm0ioctl; 326 unsigned int cm1ioctl; 327 unsigned int cm2ioctl; 328 unsigned int dt0ioctl; 329 unsigned int dt1ioctl; 330 unsigned int dt2ioctrl; 331 unsigned int dt3ioctrl; 332 unsigned int emif_sdram_config_ext; 333 }; 334 335 /** 336 * Configure DDR io control registers 337 */ 338 void config_io_ctrl(const struct ctrl_ioregs *ioregs); 339 340 struct ddr_ctrl { 341 unsigned int ddrioctrl; 342 unsigned int resv1[325]; 343 unsigned int ddrckectrl; 344 }; 345 346 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, 347 const struct ddr_data *data, const struct cmd_control *ctrl, 348 const struct emif_regs *regs, int nr); 349 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size); 350 351 #endif /* _DDR_DEFS_H */ 352