1 /*
2  * ddr_defs.h
3  *
4  * ddr specific header
5  *
6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #ifndef _DDR_DEFS_H
12 #define _DDR_DEFS_H
13 
14 #include <asm/arch/hardware.h>
15 #include <asm/emif.h>
16 
17 /* AM335X EMIF Register values */
18 #define VTP_CTRL_READY		(0x1 << 5)
19 #define VTP_CTRL_ENABLE		(0x1 << 6)
20 #define VTP_CTRL_START_EN	(0x1)
21 #ifdef CONFIG_AM43XX
22 #define DDR_CKE_CTRL_NORMAL	0x3
23 #else
24 #define DDR_CKE_CTRL_NORMAL	0x1
25 #endif
26 #define PHY_EN_DYN_PWRDN	(0x1 << 20)
27 
28 /* Micron MT47H128M16RT-25E */
29 #define MT47H128M16RT25E_EMIF_READ_LATENCY	0x100005
30 #define MT47H128M16RT25E_EMIF_TIM1		0x0666B3C9
31 #define MT47H128M16RT25E_EMIF_TIM2		0x243631CA
32 #define MT47H128M16RT25E_EMIF_TIM3		0x0000033F
33 #define MT47H128M16RT25E_EMIF_SDCFG		0x41805332
34 #define MT47H128M16RT25E_EMIF_SDREF		0x0000081a
35 #define MT47H128M16RT25E_RATIO			0x80
36 #define MT47H128M16RT25E_RD_DQS			0x12
37 #define MT47H128M16RT25E_PHY_WR_DATA		0x40
38 #define MT47H128M16RT25E_PHY_FIFO_WE		0x80
39 #define MT47H128M16RT25E_IOCTRL_VALUE		0x18B
40 
41 /* Micron MT41J128M16JT-125 */
42 #define MT41J128MJT125_EMIF_READ_LATENCY	0x100006
43 #define MT41J128MJT125_EMIF_TIM1		0x0888A39B
44 #define MT41J128MJT125_EMIF_TIM2		0x26337FDA
45 #define MT41J128MJT125_EMIF_TIM3		0x501F830F
46 #define MT41J128MJT125_EMIF_SDCFG		0x61C04AB2
47 #define MT41J128MJT125_EMIF_SDREF		0x0000093B
48 #define MT41J128MJT125_ZQ_CFG			0x50074BE4
49 #define MT41J128MJT125_RATIO			0x40
50 #define MT41J128MJT125_INVERT_CLKOUT		0x1
51 #define MT41J128MJT125_RD_DQS			0x3B
52 #define MT41J128MJT125_WR_DQS			0x85
53 #define MT41J128MJT125_PHY_WR_DATA		0xC1
54 #define MT41J128MJT125_PHY_FIFO_WE		0x100
55 #define MT41J128MJT125_IOCTRL_VALUE		0x18B
56 
57 /* Micron MT41J128M16JT-125 at 400MHz*/
58 #define MT41J128MJT125_EMIF_READ_LATENCY_400MHz	0x100007
59 #define MT41J128MJT125_EMIF_TIM1_400MHz		0x0AAAD4DB
60 #define MT41J128MJT125_EMIF_TIM2_400MHz		0x26437FDA
61 #define MT41J128MJT125_EMIF_TIM3_400MHz		0x501F83FF
62 #define MT41J128MJT125_EMIF_SDCFG_400MHz	0x61C052B2
63 #define MT41J128MJT125_EMIF_SDREF_400MHz	0x00000C30
64 #define MT41J128MJT125_ZQ_CFG_400MHz		0x50074BE4
65 #define MT41J128MJT125_RATIO_400MHz		0x80
66 #define MT41J128MJT125_INVERT_CLKOUT_400MHz	0x0
67 #define MT41J128MJT125_RD_DQS_400MHz		0x3A
68 #define MT41J128MJT125_WR_DQS_400MHz		0x3B
69 #define MT41J128MJT125_PHY_WR_DATA_400MHz	0x76
70 #define MT41J128MJT125_PHY_FIFO_WE_400MHz	0x96
71 
72 /* Micron MT41K128M16JT-187E */
73 #define MT41K128MJT187E_EMIF_READ_LATENCY	0x06
74 #define MT41K128MJT187E_EMIF_TIM1		0x0888B3DB
75 #define MT41K128MJT187E_EMIF_TIM2		0x36337FDA
76 #define MT41K128MJT187E_EMIF_TIM3		0x501F830F
77 #define MT41K128MJT187E_EMIF_SDCFG		0x61C04AB2
78 #define MT41K128MJT187E_EMIF_SDREF		0x0000093B
79 #define MT41K128MJT187E_ZQ_CFG			0x50074BE4
80 #define MT41K128MJT187E_RATIO			0x40
81 #define MT41K128MJT187E_INVERT_CLKOUT		0x1
82 #define MT41K128MJT187E_RD_DQS			0x3B
83 #define MT41K128MJT187E_WR_DQS			0x85
84 #define MT41K128MJT187E_PHY_WR_DATA		0xC1
85 #define MT41K128MJT187E_PHY_FIFO_WE		0x100
86 #define MT41K128MJT187E_IOCTRL_VALUE		0x18B
87 
88 /* Micron MT41J64M16JT-125 */
89 #define MT41J64MJT125_EMIF_SDCFG		0x61C04A32
90 
91 /* Micron MT41J256M16JT-125 */
92 #define MT41J256MJT125_EMIF_SDCFG		0x61C04B32
93 
94 /* Micron MT41J256M8HX-15E */
95 #define MT41J256M8HX15E_EMIF_READ_LATENCY	0x100006
96 #define MT41J256M8HX15E_EMIF_TIM1		0x0888A39B
97 #define MT41J256M8HX15E_EMIF_TIM2		0x26337FDA
98 #define MT41J256M8HX15E_EMIF_TIM3		0x501F830F
99 #define MT41J256M8HX15E_EMIF_SDCFG		0x61C04B32
100 #define MT41J256M8HX15E_EMIF_SDREF		0x0000093B
101 #define MT41J256M8HX15E_ZQ_CFG			0x50074BE4
102 #define MT41J256M8HX15E_RATIO			0x40
103 #define MT41J256M8HX15E_INVERT_CLKOUT		0x1
104 #define MT41J256M8HX15E_RD_DQS			0x3B
105 #define MT41J256M8HX15E_WR_DQS			0x85
106 #define MT41J256M8HX15E_PHY_WR_DATA		0xC1
107 #define MT41J256M8HX15E_PHY_FIFO_WE		0x100
108 #define MT41J256M8HX15E_IOCTRL_VALUE		0x18B
109 
110 /* Micron MT41K256M16HA-125E */
111 #define MT41K256M16HA125E_EMIF_READ_LATENCY	0x100007
112 #define MT41K256M16HA125E_EMIF_TIM1		0x0AAAD4DB
113 #define MT41K256M16HA125E_EMIF_TIM2		0x266B7FDA
114 #define MT41K256M16HA125E_EMIF_TIM3		0x501F867F
115 #define MT41K256M16HA125E_EMIF_SDCFG		0x61C05332
116 #define MT41K256M16HA125E_EMIF_SDREF		0xC30
117 #define MT41K256M16HA125E_ZQ_CFG		0x50074BE4
118 #define MT41K256M16HA125E_RATIO			0x80
119 #define MT41K256M16HA125E_INVERT_CLKOUT		0x0
120 #define MT41K256M16HA125E_RD_DQS		0x38
121 #define MT41K256M16HA125E_WR_DQS		0x44
122 #define MT41K256M16HA125E_PHY_WR_DATA		0x7D
123 #define MT41K256M16HA125E_PHY_FIFO_WE		0x94
124 #define MT41K256M16HA125E_IOCTRL_VALUE		0x18B
125 
126 /* Micron MT41J512M8RH-125 on EVM v1.5 */
127 #define MT41J512M8RH125_EMIF_READ_LATENCY	0x100006
128 #define MT41J512M8RH125_EMIF_TIM1		0x0888A39B
129 #define MT41J512M8RH125_EMIF_TIM2		0x26517FDA
130 #define MT41J512M8RH125_EMIF_TIM3		0x501F84EF
131 #define MT41J512M8RH125_EMIF_SDCFG		0x61C04BB2
132 #define MT41J512M8RH125_EMIF_SDREF		0x0000093B
133 #define MT41J512M8RH125_ZQ_CFG			0x50074BE4
134 #define MT41J512M8RH125_RATIO			0x80
135 #define MT41J512M8RH125_INVERT_CLKOUT		0x0
136 #define MT41J512M8RH125_RD_DQS			0x3B
137 #define MT41J512M8RH125_WR_DQS			0x3C
138 #define MT41J512M8RH125_PHY_FIFO_WE		0xA5
139 #define MT41J512M8RH125_PHY_WR_DATA		0x74
140 #define MT41J512M8RH125_IOCTRL_VALUE		0x18B
141 
142 /* Samsung K4B2G1646E-BIH9 */
143 #define K4B2G1646EBIH9_EMIF_READ_LATENCY	0x100007
144 #define K4B2G1646EBIH9_EMIF_TIM1		0x0AAAE51B
145 #define K4B2G1646EBIH9_EMIF_TIM2		0x2A1D7FDA
146 #define K4B2G1646EBIH9_EMIF_TIM3		0x501F83FF
147 #define K4B2G1646EBIH9_EMIF_SDCFG		0x61C052B2
148 #define K4B2G1646EBIH9_EMIF_SDREF		0x00000C30
149 #define K4B2G1646EBIH9_ZQ_CFG			0x50074BE4
150 #define K4B2G1646EBIH9_RATIO			0x80
151 #define K4B2G1646EBIH9_INVERT_CLKOUT		0x0
152 #define K4B2G1646EBIH9_RD_DQS			0x35
153 #define K4B2G1646EBIH9_WR_DQS			0x3A
154 #define K4B2G1646EBIH9_PHY_FIFO_WE		0x97
155 #define K4B2G1646EBIH9_PHY_WR_DATA		0x76
156 #define K4B2G1646EBIH9_IOCTRL_VALUE		0x18B
157 
158 #define  LPDDR2_ADDRCTRL_IOCTRL_VALUE   0x294
159 #define  LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
160 #define  LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
161 #define  LPDDR2_DATA0_IOCTRL_VALUE   0x20000294
162 #define  LPDDR2_DATA1_IOCTRL_VALUE   0x20000294
163 #define  LPDDR2_DATA2_IOCTRL_VALUE   0x20000294
164 #define  LPDDR2_DATA3_IOCTRL_VALUE   0x20000294
165 
166 #define  DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
167 #define  DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
168 #define  DDR3_ADDRCTRL_IOCTRL_VALUE   0x84
169 #define  DDR3_DATA0_IOCTRL_VALUE   0x84
170 #define  DDR3_DATA1_IOCTRL_VALUE   0x84
171 #define  DDR3_DATA2_IOCTRL_VALUE   0x84
172 #define  DDR3_DATA3_IOCTRL_VALUE   0x84
173 
174 /**
175  * Configure DMM
176  */
177 void config_dmm(const struct dmm_lisa_map_regs *regs);
178 
179 /**
180  * Configure SDRAM
181  */
182 void config_sdram(const struct emif_regs *regs, int nr);
183 void config_sdram_emif4d5(const struct emif_regs *regs, int nr);
184 
185 /**
186  * Set SDRAM timings
187  */
188 void set_sdram_timings(const struct emif_regs *regs, int nr);
189 
190 /**
191  * Configure DDR PHY
192  */
193 void config_ddr_phy(const struct emif_regs *regs, int nr);
194 
195 struct ddr_cmd_regs {
196 	unsigned int resv0[7];
197 	unsigned int cm0csratio;	/* offset 0x01C */
198 	unsigned int resv1[3];
199 	unsigned int cm0iclkout;	/* offset 0x02C */
200 	unsigned int resv2[8];
201 	unsigned int cm1csratio;	/* offset 0x050 */
202 	unsigned int resv3[3];
203 	unsigned int cm1iclkout;	/* offset 0x060 */
204 	unsigned int resv4[8];
205 	unsigned int cm2csratio;	/* offset 0x084 */
206 	unsigned int resv5[3];
207 	unsigned int cm2iclkout;	/* offset 0x094 */
208 	unsigned int resv6[3];
209 };
210 
211 struct ddr_data_regs {
212 	unsigned int dt0rdsratio0;	/* offset 0x0C8 */
213 	unsigned int resv1[4];
214 	unsigned int dt0wdsratio0;	/* offset 0x0DC */
215 	unsigned int resv2[4];
216 	unsigned int dt0wiratio0;	/* offset 0x0F0 */
217 	unsigned int resv3;
218 	unsigned int dt0wimode0;	/* offset 0x0F8 */
219 	unsigned int dt0giratio0;	/* offset 0x0FC */
220 	unsigned int resv4;
221 	unsigned int dt0gimode0;	/* offset 0x104 */
222 	unsigned int dt0fwsratio0;	/* offset 0x108 */
223 	unsigned int resv5[4];
224 	unsigned int dt0dqoffset;	/* offset 0x11C */
225 	unsigned int dt0wrsratio0;	/* offset 0x120 */
226 	unsigned int resv6[4];
227 	unsigned int dt0rdelays0;	/* offset 0x134 */
228 	unsigned int dt0dldiff0;	/* offset 0x138 */
229 	unsigned int resv7[12];
230 };
231 
232 /**
233  * This structure represents the DDR registers on AM33XX devices.
234  * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
235  * correspond to DATA1 registers defined here.
236  */
237 struct ddr_regs {
238 	unsigned int resv0[3];
239 	unsigned int cm0config;		/* offset 0x00C */
240 	unsigned int cm0configclk;	/* offset 0x010 */
241 	unsigned int resv1[2];
242 	unsigned int cm0csratio;	/* offset 0x01C */
243 	unsigned int resv2[3];
244 	unsigned int cm0iclkout;	/* offset 0x02C */
245 	unsigned int resv3[4];
246 	unsigned int cm1config;		/* offset 0x040 */
247 	unsigned int cm1configclk;	/* offset 0x044 */
248 	unsigned int resv4[2];
249 	unsigned int cm1csratio;	/* offset 0x050 */
250 	unsigned int resv5[3];
251 	unsigned int cm1iclkout;	/* offset 0x060 */
252 	unsigned int resv6[4];
253 	unsigned int cm2config;		/* offset 0x074 */
254 	unsigned int cm2configclk;	/* offset 0x078 */
255 	unsigned int resv7[2];
256 	unsigned int cm2csratio;	/* offset 0x084 */
257 	unsigned int resv8[3];
258 	unsigned int cm2iclkout;	/* offset 0x094 */
259 	unsigned int resv9[12];
260 	unsigned int dt0rdsratio0;	/* offset 0x0C8 */
261 	unsigned int resv10[4];
262 	unsigned int dt0wdsratio0;	/* offset 0x0DC */
263 	unsigned int resv11[4];
264 	unsigned int dt0wiratio0;	/* offset 0x0F0 */
265 	unsigned int resv12;
266 	unsigned int dt0wimode0;	/* offset 0x0F8 */
267 	unsigned int dt0giratio0;	/* offset 0x0FC */
268 	unsigned int resv13;
269 	unsigned int dt0gimode0;	/* offset 0x104 */
270 	unsigned int dt0fwsratio0;	/* offset 0x108 */
271 	unsigned int resv14[4];
272 	unsigned int dt0dqoffset;	/* offset 0x11C */
273 	unsigned int dt0wrsratio0;	/* offset 0x120 */
274 	unsigned int resv15[4];
275 	unsigned int dt0rdelays0;	/* offset 0x134 */
276 	unsigned int dt0dldiff0;	/* offset 0x138 */
277 };
278 
279 /**
280  * Encapsulates DDR CMD control registers.
281  */
282 struct cmd_control {
283 	unsigned long cmd0csratio;
284 	unsigned long cmd0csforce;
285 	unsigned long cmd0csdelay;
286 	unsigned long cmd0iclkout;
287 	unsigned long cmd1csratio;
288 	unsigned long cmd1csforce;
289 	unsigned long cmd1csdelay;
290 	unsigned long cmd1iclkout;
291 	unsigned long cmd2csratio;
292 	unsigned long cmd2csforce;
293 	unsigned long cmd2csdelay;
294 	unsigned long cmd2iclkout;
295 };
296 
297 /**
298  * Encapsulates DDR DATA registers.
299  */
300 struct ddr_data {
301 	unsigned long datardsratio0;
302 	unsigned long datawdsratio0;
303 	unsigned long datawiratio0;
304 	unsigned long datagiratio0;
305 	unsigned long datafwsratio0;
306 	unsigned long datawrsratio0;
307 };
308 
309 /**
310  * Configure DDR CMD control registers
311  */
312 void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
313 
314 /**
315  * Configure DDR DATA registers
316  */
317 void config_ddr_data(const struct ddr_data *data, int nr);
318 
319 /**
320  * This structure represents the DDR io control on AM33XX devices.
321  */
322 struct ddr_cmdtctrl {
323 	unsigned int cm0ioctl;
324 	unsigned int cm1ioctl;
325 	unsigned int cm2ioctl;
326 	unsigned int resv2[12];
327 	unsigned int dt0ioctl;
328 	unsigned int dt1ioctl;
329 	unsigned int dt2ioctrl;
330 	unsigned int dt3ioctrl;
331 	unsigned int resv3[4];
332 	unsigned int emif_sdram_config_ext;
333 };
334 
335 struct ctrl_ioregs {
336 	unsigned int cm0ioctl;
337 	unsigned int cm1ioctl;
338 	unsigned int cm2ioctl;
339 	unsigned int dt0ioctl;
340 	unsigned int dt1ioctl;
341 	unsigned int dt2ioctrl;
342 	unsigned int dt3ioctrl;
343 	unsigned int emif_sdram_config_ext;
344 };
345 
346 /**
347  * Configure DDR io control registers
348  */
349 void config_io_ctrl(const struct ctrl_ioregs *ioregs);
350 
351 struct ddr_ctrl {
352 	unsigned int ddrioctrl;
353 	unsigned int resv1[325];
354 	unsigned int ddrckectrl;
355 };
356 
357 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
358 		const struct ddr_data *data, const struct cmd_control *ctrl,
359 		const struct emif_regs *regs, int nr);
360 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
361 
362 #endif  /* _DDR_DEFS_H */
363