1 /*
2  * ddr_defs.h
3  *
4  * ddr specific header
5  *
6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18 
19 #ifndef _DDR_DEFS_H
20 #define _DDR_DEFS_H
21 
22 #include <asm/arch/hardware.h>
23 #include <asm/emif.h>
24 
25 /* AM335X EMIF Register values */
26 #define VTP_CTRL_READY		(0x1 << 5)
27 #define VTP_CTRL_ENABLE		(0x1 << 6)
28 #define VTP_CTRL_START_EN	(0x1)
29 #define PHY_DLL_LOCK_DIFF	0x0
30 #define DDR_CKE_CTRL_NORMAL	0x1
31 #define PHY_EN_DYN_PWRDN	(0x1 << 20)
32 
33 /* Micron MT47H128M16RT-25E */
34 #define MT47H128M16RT25E_EMIF_READ_LATENCY	0x100005
35 #define MT47H128M16RT25E_EMIF_TIM1		0x0666B3C9
36 #define MT47H128M16RT25E_EMIF_TIM2		0x243631CA
37 #define MT47H128M16RT25E_EMIF_TIM3		0x0000033F
38 #define MT47H128M16RT25E_EMIF_SDCFG		0x41805332
39 #define MT47H128M16RT25E_EMIF_SDREF		0x0000081a
40 #define MT47H128M16RT25E_DLL_LOCK_DIFF		0x0
41 #define MT47H128M16RT25E_RATIO			0x80
42 #define MT47H128M16RT25E_INVERT_CLKOUT		0x00
43 #define MT47H128M16RT25E_RD_DQS			0x12
44 #define MT47H128M16RT25E_WR_DQS			0x00
45 #define MT47H128M16RT25E_PHY_WRLVL		0x00
46 #define MT47H128M16RT25E_PHY_GATELVL		0x00
47 #define MT47H128M16RT25E_PHY_WR_DATA		0x40
48 #define MT47H128M16RT25E_PHY_FIFO_WE		0x80
49 #define MT47H128M16RT25E_PHY_RANK0_DELAY		0x1
50 #define MT47H128M16RT25E_IOCTRL_VALUE		0x18B
51 
52 /* Micron MT41J128M16JT-125 */
53 #define MT41J128MJT125_EMIF_READ_LATENCY	0x06
54 #define MT41J128MJT125_EMIF_TIM1		0x0888A39B
55 #define MT41J128MJT125_EMIF_TIM2		0x26337FDA
56 #define MT41J128MJT125_EMIF_TIM3		0x501F830F
57 #define MT41J128MJT125_EMIF_SDCFG		0x61C04AB2
58 #define MT41J128MJT125_EMIF_SDREF		0x0000093B
59 #define MT41J128MJT125_ZQ_CFG			0x50074BE4
60 #define MT41J128MJT125_DLL_LOCK_DIFF		0x1
61 #define MT41J128MJT125_RATIO			0x40
62 #define MT41J128MJT125_INVERT_CLKOUT		0x1
63 #define MT41J128MJT125_RD_DQS			0x3B
64 #define MT41J128MJT125_WR_DQS			0x85
65 #define MT41J128MJT125_PHY_WR_DATA		0xC1
66 #define MT41J128MJT125_PHY_FIFO_WE		0x100
67 #define MT41J128MJT125_IOCTRL_VALUE		0x18B
68 
69 /* Micron MT41J256M8HX-15E */
70 #define MT41J256M8HX15E_EMIF_READ_LATENCY	0x06
71 #define MT41J256M8HX15E_EMIF_TIM1		0x0888A39B
72 #define MT41J256M8HX15E_EMIF_TIM2		0x26337FDA
73 #define MT41J256M8HX15E_EMIF_TIM3		0x501F830F
74 #define MT41J256M8HX15E_EMIF_SDCFG		0x61C04B32
75 #define MT41J256M8HX15E_EMIF_SDREF		0x0000093B
76 #define MT41J256M8HX15E_ZQ_CFG			0x50074BE4
77 #define MT41J256M8HX15E_DLL_LOCK_DIFF		0x1
78 #define MT41J256M8HX15E_RATIO			0x40
79 #define MT41J256M8HX15E_INVERT_CLKOUT		0x1
80 #define MT41J256M8HX15E_RD_DQS			0x3B
81 #define MT41J256M8HX15E_WR_DQS			0x85
82 #define MT41J256M8HX15E_PHY_WR_DATA		0xC1
83 #define MT41J256M8HX15E_PHY_FIFO_WE		0x100
84 #define MT41J256M8HX15E_IOCTRL_VALUE		0x18B
85 
86 /* Micron MT41K256M16HA-125E */
87 #define MT41K256M16HA125E_EMIF_READ_LATENCY	0x100007
88 #define MT41K256M16HA125E_EMIF_TIM1		0x0AAAD4DB
89 #define MT41K256M16HA125E_EMIF_TIM2		0x266B7FDA
90 #define MT41K256M16HA125E_EMIF_TIM3		0x501F867F
91 #define MT41K256M16HA125E_EMIF_SDCFG		0x61C05332
92 #define MT41K256M16HA125E_EMIF_SDREF		0xC30
93 #define MT41K256M16HA125E_ZQ_CFG		0x50074BE4
94 #define MT41K256M16HA125E_DLL_LOCK_DIFF		0x1
95 #define MT41K256M16HA125E_RATIO			0x80
96 #define MT41K256M16HA125E_INVERT_CLKOUT		0x0
97 #define MT41K256M16HA125E_RD_DQS		0x38
98 #define MT41K256M16HA125E_WR_DQS		0x44
99 #define MT41K256M16HA125E_PHY_WR_DATA		0x7D
100 #define MT41K256M16HA125E_PHY_FIFO_WE		0x94
101 #define MT41K256M16HA125E_IOCTRL_VALUE		0x18B
102 
103 /* Micron MT41J512M8RH-125 on EVM v1.5 */
104 #define MT41J512M8RH125_EMIF_READ_LATENCY	0x06
105 #define MT41J512M8RH125_EMIF_TIM1		0x0888A39B
106 #define MT41J512M8RH125_EMIF_TIM2		0x26517FDA
107 #define MT41J512M8RH125_EMIF_TIM3		0x501F84EF
108 #define MT41J512M8RH125_EMIF_SDCFG		0x61C04BB2
109 #define MT41J512M8RH125_EMIF_SDREF		0x0000093B
110 #define MT41J512M8RH125_ZQ_CFG			0x50074BE4
111 #define MT41J512M8RH125_DLL_LOCK_DIFF		0x1
112 #define MT41J512M8RH125_RATIO			0x80
113 #define MT41J512M8RH125_INVERT_CLKOUT		0x0
114 #define MT41J512M8RH125_RD_DQS			0x3B
115 #define MT41J512M8RH125_WR_DQS			0x3C
116 #define MT41J512M8RH125_PHY_FIFO_WE		0xA5
117 #define MT41J512M8RH125_PHY_WR_DATA		0x74
118 #define MT41J512M8RH125_IOCTRL_VALUE		0x18B
119 
120 /**
121  * Configure DMM
122  */
123 void config_dmm(const struct dmm_lisa_map_regs *regs);
124 
125 /**
126  * Configure SDRAM
127  */
128 void config_sdram(const struct emif_regs *regs, int nr);
129 
130 /**
131  * Set SDRAM timings
132  */
133 void set_sdram_timings(const struct emif_regs *regs, int nr);
134 
135 /**
136  * Configure DDR PHY
137  */
138 void config_ddr_phy(const struct emif_regs *regs, int nr);
139 
140 struct ddr_cmd_regs {
141 	unsigned int resv0[7];
142 	unsigned int cm0csratio;	/* offset 0x01C */
143 	unsigned int resv1[2];
144 	unsigned int cm0dldiff;		/* offset 0x028 */
145 	unsigned int cm0iclkout;	/* offset 0x02C */
146 	unsigned int resv2[8];
147 	unsigned int cm1csratio;	/* offset 0x050 */
148 	unsigned int resv3[2];
149 	unsigned int cm1dldiff;		/* offset 0x05C */
150 	unsigned int cm1iclkout;	/* offset 0x060 */
151 	unsigned int resv4[8];
152 	unsigned int cm2csratio;	/* offset 0x084 */
153 	unsigned int resv5[2];
154 	unsigned int cm2dldiff;		/* offset 0x090 */
155 	unsigned int cm2iclkout;	/* offset 0x094 */
156 	unsigned int resv6[3];
157 };
158 
159 struct ddr_data_regs {
160 	unsigned int dt0rdsratio0;	/* offset 0x0C8 */
161 	unsigned int resv1[4];
162 	unsigned int dt0wdsratio0;	/* offset 0x0DC */
163 	unsigned int resv2[4];
164 	unsigned int dt0wiratio0;	/* offset 0x0F0 */
165 	unsigned int resv3;
166 	unsigned int dt0wimode0;	/* offset 0x0F8 */
167 	unsigned int dt0giratio0;	/* offset 0x0FC */
168 	unsigned int resv4;
169 	unsigned int dt0gimode0;	/* offset 0x104 */
170 	unsigned int dt0fwsratio0;	/* offset 0x108 */
171 	unsigned int resv5[4];
172 	unsigned int dt0dqoffset;	/* offset 0x11C */
173 	unsigned int dt0wrsratio0;	/* offset 0x120 */
174 	unsigned int resv6[4];
175 	unsigned int dt0rdelays0;	/* offset 0x134 */
176 	unsigned int dt0dldiff0;	/* offset 0x138 */
177 	unsigned int resv7[12];
178 };
179 
180 /**
181  * This structure represents the DDR registers on AM33XX devices.
182  * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
183  * correspond to DATA1 registers defined here.
184  */
185 struct ddr_regs {
186 	unsigned int resv0[7];
187 	unsigned int cm0csratio;	/* offset 0x01C */
188 	unsigned int resv1[2];
189 	unsigned int cm0dldiff;		/* offset 0x028 */
190 	unsigned int cm0iclkout;	/* offset 0x02C */
191 	unsigned int resv2[8];
192 	unsigned int cm1csratio;	/* offset 0x050 */
193 	unsigned int resv3[2];
194 	unsigned int cm1dldiff;		/* offset 0x05C */
195 	unsigned int cm1iclkout;	/* offset 0x060 */
196 	unsigned int resv4[8];
197 	unsigned int cm2csratio;	/* offset 0x084 */
198 	unsigned int resv5[2];
199 	unsigned int cm2dldiff;		/* offset 0x090 */
200 	unsigned int cm2iclkout;	/* offset 0x094 */
201 	unsigned int resv6[12];
202 	unsigned int dt0rdsratio0;	/* offset 0x0C8 */
203 	unsigned int resv7[4];
204 	unsigned int dt0wdsratio0;	/* offset 0x0DC */
205 	unsigned int resv8[4];
206 	unsigned int dt0wiratio0;	/* offset 0x0F0 */
207 	unsigned int resv9;
208 	unsigned int dt0wimode0;	/* offset 0x0F8 */
209 	unsigned int dt0giratio0;	/* offset 0x0FC */
210 	unsigned int resv10;
211 	unsigned int dt0gimode0;	/* offset 0x104 */
212 	unsigned int dt0fwsratio0;	/* offset 0x108 */
213 	unsigned int resv11[4];
214 	unsigned int dt0dqoffset;	/* offset 0x11C */
215 	unsigned int dt0wrsratio0;	/* offset 0x120 */
216 	unsigned int resv12[4];
217 	unsigned int dt0rdelays0;	/* offset 0x134 */
218 	unsigned int dt0dldiff0;	/* offset 0x138 */
219 };
220 
221 /**
222  * Encapsulates DDR CMD control registers.
223  */
224 struct cmd_control {
225 	unsigned long cmd0csratio;
226 	unsigned long cmd0csforce;
227 	unsigned long cmd0csdelay;
228 	unsigned long cmd0dldiff;
229 	unsigned long cmd0iclkout;
230 	unsigned long cmd1csratio;
231 	unsigned long cmd1csforce;
232 	unsigned long cmd1csdelay;
233 	unsigned long cmd1dldiff;
234 	unsigned long cmd1iclkout;
235 	unsigned long cmd2csratio;
236 	unsigned long cmd2csforce;
237 	unsigned long cmd2csdelay;
238 	unsigned long cmd2dldiff;
239 	unsigned long cmd2iclkout;
240 };
241 
242 /**
243  * Encapsulates DDR DATA registers.
244  */
245 struct ddr_data {
246 	unsigned long datardsratio0;
247 	unsigned long datawdsratio0;
248 	unsigned long datawiratio0;
249 	unsigned long datagiratio0;
250 	unsigned long datafwsratio0;
251 	unsigned long datawrsratio0;
252 	unsigned long datauserank0delay;
253 	unsigned long datadldiff0;
254 };
255 
256 /**
257  * Configure DDR CMD control registers
258  */
259 void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
260 
261 /**
262  * Configure DDR DATA registers
263  */
264 void config_ddr_data(const struct ddr_data *data, int nr);
265 
266 /**
267  * This structure represents the DDR io control on AM33XX devices.
268  */
269 struct ddr_cmdtctrl {
270 	unsigned int resv1[1];
271 	unsigned int cm0ioctl;
272 	unsigned int cm1ioctl;
273 	unsigned int cm2ioctl;
274 	unsigned int resv2[12];
275 	unsigned int dt0ioctl;
276 	unsigned int dt1ioctl;
277 };
278 
279 /**
280  * Configure DDR io control registers
281  */
282 void config_io_ctrl(unsigned long val);
283 
284 struct ddr_ctrl {
285 	unsigned int ddrioctrl;
286 	unsigned int resv1[325];
287 	unsigned int ddrckectrl;
288 };
289 
290 void config_ddr(unsigned int pll, unsigned int ioctrl,
291 		const struct ddr_data *data, const struct cmd_control *ctrl,
292 		const struct emif_regs *regs, int nr);
293 
294 #endif  /* _DDR_DEFS_H */
295