1 /* 2 * ddr_defs.h 3 * 4 * ddr specific header 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef _DDR_DEFS_H 20 #define _DDR_DEFS_H 21 22 #include <asm/arch/hardware.h> 23 #include <asm/emif.h> 24 25 /* AM335X EMIF Register values */ 26 #define VTP_CTRL_READY (0x1 << 5) 27 #define VTP_CTRL_ENABLE (0x1 << 6) 28 #define VTP_CTRL_START_EN (0x1) 29 #define PHY_DLL_LOCK_DIFF 0x0 30 #define DDR_CKE_CTRL_NORMAL 0x1 31 32 #define DDR2_EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */ 33 #define DDR2_EMIF_TIM1 0x0666B3C9 34 #define DDR2_EMIF_TIM2 0x243631CA 35 #define DDR2_EMIF_TIM3 0x0000033F 36 #define DDR2_EMIF_SDCFG 0x41805332 37 #define DDR2_EMIF_SDREF 0x0000081a 38 #define DDR2_DLL_LOCK_DIFF 0x0 39 #define DDR2_RATIO 0x80 40 #define DDR2_INVERT_CLKOUT 0x00 41 #define DDR2_RD_DQS 0x12 42 #define DDR2_WR_DQS 0x00 43 #define DDR2_PHY_WRLVL 0x00 44 #define DDR2_PHY_GATELVL 0x00 45 #define DDR2_PHY_WR_DATA 0x40 46 #define DDR2_PHY_FIFO_WE 0x80 47 #define DDR2_PHY_RANK0_DELAY 0x1 48 #define DDR2_IOCTRL_VALUE 0x18B 49 50 /* Micron MT41J128M16JT-125 */ 51 #define DDR3_EMIF_READ_LATENCY 0x06 52 #define DDR3_EMIF_TIM1 0x0888A39B 53 #define DDR3_EMIF_TIM2 0x26337FDA 54 #define DDR3_EMIF_TIM3 0x501F830F 55 #define DDR3_EMIF_SDCFG 0x61C04AB2 56 #define DDR3_EMIF_SDREF 0x0000093B 57 #define DDR3_ZQ_CFG 0x50074BE4 58 #define DDR3_DLL_LOCK_DIFF 0x1 59 #define DDR3_RATIO 0x40 60 #define DDR3_INVERT_CLKOUT 0x1 61 #define DDR3_RD_DQS 0x3B 62 #define DDR3_WR_DQS 0x85 63 #define DDR3_PHY_WR_DATA 0xC1 64 #define DDR3_PHY_FIFO_WE 0x100 65 #define DDR3_IOCTRL_VALUE 0x18B 66 67 /** 68 * Configure SDRAM 69 */ 70 void config_sdram(const struct emif_regs *regs); 71 72 /** 73 * Set SDRAM timings 74 */ 75 void set_sdram_timings(const struct emif_regs *regs); 76 77 /** 78 * Configure DDR PHY 79 */ 80 void config_ddr_phy(const struct emif_regs *regs); 81 82 /** 83 * This structure represents the DDR registers on AM33XX devices. 84 * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that 85 * correspond to DATA1 registers defined here. 86 */ 87 struct ddr_regs { 88 unsigned int resv0[7]; 89 unsigned int cm0csratio; /* offset 0x01C */ 90 unsigned int resv1[2]; 91 unsigned int cm0dldiff; /* offset 0x028 */ 92 unsigned int cm0iclkout; /* offset 0x02C */ 93 unsigned int resv2[8]; 94 unsigned int cm1csratio; /* offset 0x050 */ 95 unsigned int resv3[2]; 96 unsigned int cm1dldiff; /* offset 0x05C */ 97 unsigned int cm1iclkout; /* offset 0x060 */ 98 unsigned int resv4[8]; 99 unsigned int cm2csratio; /* offset 0x084 */ 100 unsigned int resv5[2]; 101 unsigned int cm2dldiff; /* offset 0x090 */ 102 unsigned int cm2iclkout; /* offset 0x094 */ 103 unsigned int resv6[12]; 104 unsigned int dt0rdsratio0; /* offset 0x0C8 */ 105 unsigned int resv7[4]; 106 unsigned int dt0wdsratio0; /* offset 0x0DC */ 107 unsigned int resv8[4]; 108 unsigned int dt0wiratio0; /* offset 0x0F0 */ 109 unsigned int resv9; 110 unsigned int dt0wimode0; /* offset 0x0F8 */ 111 unsigned int dt0giratio0; /* offset 0x0FC */ 112 unsigned int resv10; 113 unsigned int dt0gimode0; /* offset 0x104 */ 114 unsigned int dt0fwsratio0; /* offset 0x108 */ 115 unsigned int resv11[4]; 116 unsigned int dt0dqoffset; /* offset 0x11C */ 117 unsigned int dt0wrsratio0; /* offset 0x120 */ 118 unsigned int resv12[4]; 119 unsigned int dt0rdelays0; /* offset 0x134 */ 120 unsigned int dt0dldiff0; /* offset 0x138 */ 121 }; 122 123 /** 124 * Encapsulates DDR CMD control registers. 125 */ 126 struct cmd_control { 127 unsigned long cmd0csratio; 128 unsigned long cmd0csforce; 129 unsigned long cmd0csdelay; 130 unsigned long cmd0dldiff; 131 unsigned long cmd0iclkout; 132 unsigned long cmd1csratio; 133 unsigned long cmd1csforce; 134 unsigned long cmd1csdelay; 135 unsigned long cmd1dldiff; 136 unsigned long cmd1iclkout; 137 unsigned long cmd2csratio; 138 unsigned long cmd2csforce; 139 unsigned long cmd2csdelay; 140 unsigned long cmd2dldiff; 141 unsigned long cmd2iclkout; 142 }; 143 144 /** 145 * Encapsulates DDR DATA registers. 146 */ 147 struct ddr_data { 148 unsigned long datardsratio0; 149 unsigned long datawdsratio0; 150 unsigned long datawiratio0; 151 unsigned long datagiratio0; 152 unsigned long datafwsratio0; 153 unsigned long datawrsratio0; 154 unsigned long datauserank0delay; 155 unsigned long datadldiff0; 156 }; 157 158 /** 159 * Configure DDR CMD control registers 160 */ 161 void config_cmd_ctrl(const struct cmd_control *cmd); 162 163 /** 164 * Configure DDR DATA registers 165 */ 166 void config_ddr_data(int data_macrono, const struct ddr_data *data); 167 168 /** 169 * This structure represents the DDR io control on AM33XX devices. 170 */ 171 struct ddr_cmdtctrl { 172 unsigned int resv1[1]; 173 unsigned int cm0ioctl; 174 unsigned int cm1ioctl; 175 unsigned int cm2ioctl; 176 unsigned int resv2[12]; 177 unsigned int dt0ioctl; 178 unsigned int dt1ioctl; 179 }; 180 181 /** 182 * Configure DDR io control registers 183 */ 184 void config_io_ctrl(unsigned long val); 185 186 struct ddr_ctrl { 187 unsigned int ddrioctrl; 188 unsigned int resv1[325]; 189 unsigned int ddrckectrl; 190 }; 191 192 void config_ddr(short ddr_type); 193 194 #endif /* _DDR_DEFS_H */ 195