1 /* 2 * ddr_defs.h 3 * 4 * ddr specific header 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef _DDR_DEFS_H 20 #define _DDR_DEFS_H 21 22 #include <asm/arch/hardware.h> 23 #include <asm/emif.h> 24 25 /* AM335X EMIF Register values */ 26 #define VTP_CTRL_READY (0x1 << 5) 27 #define VTP_CTRL_ENABLE (0x1 << 6) 28 #define VTP_CTRL_START_EN (0x1) 29 #define PHY_DLL_LOCK_DIFF 0x0 30 #define DDR_CKE_CTRL_NORMAL 0x1 31 32 /* Micron MT47H128M16RT-25E */ 33 #define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005 34 #define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9 35 #define MT47H128M16RT25E_EMIF_TIM2 0x243631CA 36 #define MT47H128M16RT25E_EMIF_TIM3 0x0000033F 37 #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 38 #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a 39 #define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0 40 #define MT47H128M16RT25E_RATIO 0x80 41 #define MT47H128M16RT25E_INVERT_CLKOUT 0x00 42 #define MT47H128M16RT25E_RD_DQS 0x12 43 #define MT47H128M16RT25E_WR_DQS 0x00 44 #define MT47H128M16RT25E_PHY_WRLVL 0x00 45 #define MT47H128M16RT25E_PHY_GATELVL 0x00 46 #define MT47H128M16RT25E_PHY_WR_DATA 0x40 47 #define MT47H128M16RT25E_PHY_FIFO_WE 0x80 48 #define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1 49 #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B 50 51 /* Micron MT41J128M16JT-125 */ 52 #define MT41J128MJT125_EMIF_READ_LATENCY 0x06 53 #define MT41J128MJT125_EMIF_TIM1 0x0888A39B 54 #define MT41J128MJT125_EMIF_TIM2 0x26337FDA 55 #define MT41J128MJT125_EMIF_TIM3 0x501F830F 56 #define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2 57 #define MT41J128MJT125_EMIF_SDREF 0x0000093B 58 #define MT41J128MJT125_ZQ_CFG 0x50074BE4 59 #define MT41J128MJT125_DLL_LOCK_DIFF 0x1 60 #define MT41J128MJT125_RATIO 0x40 61 #define MT41J128MJT125_INVERT_CLKOUT 0x1 62 #define MT41J128MJT125_RD_DQS 0x3B 63 #define MT41J128MJT125_WR_DQS 0x85 64 #define MT41J128MJT125_PHY_WR_DATA 0xC1 65 #define MT41J128MJT125_PHY_FIFO_WE 0x100 66 #define MT41J128MJT125_IOCTRL_VALUE 0x18B 67 68 /* Micron MT41J256M8HX-15E */ 69 #define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06 70 #define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B 71 #define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA 72 #define MT41J256M8HX15E_EMIF_TIM3 0x501F830F 73 #define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32 74 #define MT41J256M8HX15E_EMIF_SDREF 0x0000093B 75 #define MT41J256M8HX15E_ZQ_CFG 0x50074BE4 76 #define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1 77 #define MT41J256M8HX15E_RATIO 0x40 78 #define MT41J256M8HX15E_INVERT_CLKOUT 0x1 79 #define MT41J256M8HX15E_RD_DQS 0x3B 80 #define MT41J256M8HX15E_WR_DQS 0x85 81 #define MT41J256M8HX15E_PHY_WR_DATA 0xC1 82 #define MT41J256M8HX15E_PHY_FIFO_WE 0x100 83 #define MT41J256M8HX15E_IOCTRL_VALUE 0x18B 84 85 /* Micron MT41J512M8RH-125 on EVM v1.5 */ 86 #define MT41J512M8RH125_EMIF_READ_LATENCY 0x06 87 #define MT41J512M8RH125_EMIF_TIM1 0x0888A39B 88 #define MT41J512M8RH125_EMIF_TIM2 0x26517FDA 89 #define MT41J512M8RH125_EMIF_TIM3 0x501F84EF 90 #define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2 91 #define MT41J512M8RH125_EMIF_SDREF 0x0000093B 92 #define MT41J512M8RH125_ZQ_CFG 0x50074BE4 93 #define MT41J512M8RH125_DLL_LOCK_DIFF 0x1 94 #define MT41J512M8RH125_RATIO 0x80 95 #define MT41J512M8RH125_INVERT_CLKOUT 0x0 96 #define MT41J512M8RH125_RD_DQS 0x3B 97 #define MT41J512M8RH125_WR_DQS 0x3C 98 #define MT41J512M8RH125_PHY_FIFO_WE 0xA5 99 #define MT41J512M8RH125_PHY_WR_DATA 0x74 100 #define MT41J512M8RH125_IOCTRL_VALUE 0x18B 101 102 /** 103 * Configure SDRAM 104 */ 105 void config_sdram(const struct emif_regs *regs); 106 107 /** 108 * Set SDRAM timings 109 */ 110 void set_sdram_timings(const struct emif_regs *regs); 111 112 /** 113 * Configure DDR PHY 114 */ 115 void config_ddr_phy(const struct emif_regs *regs); 116 117 /** 118 * This structure represents the DDR registers on AM33XX devices. 119 * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that 120 * correspond to DATA1 registers defined here. 121 */ 122 struct ddr_regs { 123 unsigned int resv0[7]; 124 unsigned int cm0csratio; /* offset 0x01C */ 125 unsigned int resv1[2]; 126 unsigned int cm0dldiff; /* offset 0x028 */ 127 unsigned int cm0iclkout; /* offset 0x02C */ 128 unsigned int resv2[8]; 129 unsigned int cm1csratio; /* offset 0x050 */ 130 unsigned int resv3[2]; 131 unsigned int cm1dldiff; /* offset 0x05C */ 132 unsigned int cm1iclkout; /* offset 0x060 */ 133 unsigned int resv4[8]; 134 unsigned int cm2csratio; /* offset 0x084 */ 135 unsigned int resv5[2]; 136 unsigned int cm2dldiff; /* offset 0x090 */ 137 unsigned int cm2iclkout; /* offset 0x094 */ 138 unsigned int resv6[12]; 139 unsigned int dt0rdsratio0; /* offset 0x0C8 */ 140 unsigned int resv7[4]; 141 unsigned int dt0wdsratio0; /* offset 0x0DC */ 142 unsigned int resv8[4]; 143 unsigned int dt0wiratio0; /* offset 0x0F0 */ 144 unsigned int resv9; 145 unsigned int dt0wimode0; /* offset 0x0F8 */ 146 unsigned int dt0giratio0; /* offset 0x0FC */ 147 unsigned int resv10; 148 unsigned int dt0gimode0; /* offset 0x104 */ 149 unsigned int dt0fwsratio0; /* offset 0x108 */ 150 unsigned int resv11[4]; 151 unsigned int dt0dqoffset; /* offset 0x11C */ 152 unsigned int dt0wrsratio0; /* offset 0x120 */ 153 unsigned int resv12[4]; 154 unsigned int dt0rdelays0; /* offset 0x134 */ 155 unsigned int dt0dldiff0; /* offset 0x138 */ 156 }; 157 158 /** 159 * Encapsulates DDR CMD control registers. 160 */ 161 struct cmd_control { 162 unsigned long cmd0csratio; 163 unsigned long cmd0csforce; 164 unsigned long cmd0csdelay; 165 unsigned long cmd0dldiff; 166 unsigned long cmd0iclkout; 167 unsigned long cmd1csratio; 168 unsigned long cmd1csforce; 169 unsigned long cmd1csdelay; 170 unsigned long cmd1dldiff; 171 unsigned long cmd1iclkout; 172 unsigned long cmd2csratio; 173 unsigned long cmd2csforce; 174 unsigned long cmd2csdelay; 175 unsigned long cmd2dldiff; 176 unsigned long cmd2iclkout; 177 }; 178 179 /** 180 * Encapsulates DDR DATA registers. 181 */ 182 struct ddr_data { 183 unsigned long datardsratio0; 184 unsigned long datawdsratio0; 185 unsigned long datawiratio0; 186 unsigned long datagiratio0; 187 unsigned long datafwsratio0; 188 unsigned long datawrsratio0; 189 unsigned long datauserank0delay; 190 unsigned long datadldiff0; 191 }; 192 193 /** 194 * Configure DDR CMD control registers 195 */ 196 void config_cmd_ctrl(const struct cmd_control *cmd); 197 198 /** 199 * Configure DDR DATA registers 200 */ 201 void config_ddr_data(int data_macrono, const struct ddr_data *data); 202 203 /** 204 * This structure represents the DDR io control on AM33XX devices. 205 */ 206 struct ddr_cmdtctrl { 207 unsigned int resv1[1]; 208 unsigned int cm0ioctl; 209 unsigned int cm1ioctl; 210 unsigned int cm2ioctl; 211 unsigned int resv2[12]; 212 unsigned int dt0ioctl; 213 unsigned int dt1ioctl; 214 }; 215 216 /** 217 * Configure DDR io control registers 218 */ 219 void config_io_ctrl(unsigned long val); 220 221 struct ddr_ctrl { 222 unsigned int ddrioctrl; 223 unsigned int resv1[325]; 224 unsigned int ddrckectrl; 225 }; 226 227 void config_ddr(unsigned int pll, unsigned int ioctrl, 228 const struct ddr_data *data, const struct cmd_control *ctrl, 229 const struct emif_regs *regs); 230 231 #endif /* _DDR_DEFS_H */ 232