1 /* 2 * cpu.h 3 * 4 * AM33xx specific header file 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _AM33XX_CPU_H 12 #define _AM33XX_CPU_H 13 14 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 15 #include <asm/types.h> 16 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 17 18 #include <asm/arch/hardware.h> 19 20 #define CL_BIT(x) (0 << x) 21 22 /* Timer register bits */ 23 #define TCLR_ST BIT(0) /* Start=1 Stop=0 */ 24 #define TCLR_AR BIT(1) /* Auto reload */ 25 #define TCLR_PRE BIT(5) /* Pre-scaler enable */ 26 #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */ 27 #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */ 28 #define TCLR_CE BIT(6) /* compare mode enable */ 29 #define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */ 30 #define TCLR_TCM BIT(8) /* edge detection of input pin*/ 31 #define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */ 32 #define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/ 33 #define TCLR_CAPTMODE BIT(13) /* capture mode */ 34 #define TCLR_GPOCFG BIT(14) /* 0=output,1=input */ 35 36 #define TCFG_RESET BIT(0) /* software reset */ 37 #define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */ 38 #define TCFG_IDLEMOD_SHIFT (2) /* power management */ 39 /* device type */ 40 #define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) 41 #define TST_DEVICE 0x0 42 #define EMU_DEVICE 0x1 43 #define HS_DEVICE 0x2 44 #define GP_DEVICE 0x3 45 46 /* cpu-id for AM33XX and TI81XX family */ 47 #define AM335X 0xB944 48 #define TI81XX 0xB81E 49 #define DEVICE_ID (CTRL_BASE + 0x0600) 50 #define DEVICE_ID_MASK 0x1FFF 51 52 /* MPU max frequencies */ 53 #define AM335X_ZCZ_300 0x1FEF 54 #define AM335X_ZCZ_600 0x1FAF 55 #define AM335X_ZCZ_720 0x1F2F 56 #define AM335X_ZCZ_800 0x1E2F 57 #define AM335X_ZCZ_1000 0x1C2F 58 #define AM335X_ZCE_300 0x1FDF 59 #define AM335X_ZCE_600 0x1F9F 60 61 /* This gives the status of the boot mode pins on the evm */ 62 #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ 63 | BIT(3) | BIT(4)) 64 65 #define PRM_RSTCTRL_RESET 0x01 66 #define PRM_RSTST_WARM_RESET_MASK 0x232 67 68 /* 69 * Watchdog: 70 * Using the prescaler, the OMAP watchdog could go for many 71 * months before firing. These limits work without scaling, 72 * with the 60 second default assumed by most tools and docs. 73 */ 74 #define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */ 75 #define TIMER_MARGIN_DEFAULT 60 /* 60 secs */ 76 #define TIMER_MARGIN_MIN 1 77 78 #define PTV 0 /* prescale */ 79 #define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1) 80 #define WDT_WWPS_PEND_WCLR BIT(0) 81 #define WDT_WWPS_PEND_WLDR BIT(2) 82 #define WDT_WWPS_PEND_WTGR BIT(3) 83 #define WDT_WWPS_PEND_WSPR BIT(4) 84 85 #define WDT_WCLR_PRE BIT(5) 86 #define WDT_WCLR_PTV_OFF 2 87 88 #ifndef __KERNEL_STRICT_NAMES 89 #ifndef __ASSEMBLY__ 90 91 92 #ifndef CONFIG_AM43XX 93 /* Encapsulating core pll registers */ 94 struct cm_wkuppll { 95 unsigned int wkclkstctrl; /* offset 0x00 */ 96 unsigned int wkctrlclkctrl; /* offset 0x04 */ 97 unsigned int wkgpio0clkctrl; /* offset 0x08 */ 98 unsigned int wkl4wkclkctrl; /* offset 0x0c */ 99 unsigned int timer0clkctrl; /* offset 0x10 */ 100 unsigned int resv2[3]; 101 unsigned int idlestdpllmpu; /* offset 0x20 */ 102 unsigned int resv3[2]; 103 unsigned int clkseldpllmpu; /* offset 0x2c */ 104 unsigned int resv4[1]; 105 unsigned int idlestdpllddr; /* offset 0x34 */ 106 unsigned int resv5[2]; 107 unsigned int clkseldpllddr; /* offset 0x40 */ 108 unsigned int resv6[4]; 109 unsigned int clkseldplldisp; /* offset 0x54 */ 110 unsigned int resv7[1]; 111 unsigned int idlestdpllcore; /* offset 0x5c */ 112 unsigned int resv8[2]; 113 unsigned int clkseldpllcore; /* offset 0x68 */ 114 unsigned int resv9[1]; 115 unsigned int idlestdpllper; /* offset 0x70 */ 116 unsigned int resv10[2]; 117 unsigned int clkdcoldodpllper; /* offset 0x7c */ 118 unsigned int divm4dpllcore; /* offset 0x80 */ 119 unsigned int divm5dpllcore; /* offset 0x84 */ 120 unsigned int clkmoddpllmpu; /* offset 0x88 */ 121 unsigned int clkmoddpllper; /* offset 0x8c */ 122 unsigned int clkmoddpllcore; /* offset 0x90 */ 123 unsigned int clkmoddpllddr; /* offset 0x94 */ 124 unsigned int clkmoddplldisp; /* offset 0x98 */ 125 unsigned int clkseldpllper; /* offset 0x9c */ 126 unsigned int divm2dpllddr; /* offset 0xA0 */ 127 unsigned int divm2dplldisp; /* offset 0xA4 */ 128 unsigned int divm2dpllmpu; /* offset 0xA8 */ 129 unsigned int divm2dpllper; /* offset 0xAC */ 130 unsigned int resv11[1]; 131 unsigned int wkup_uart0ctrl; /* offset 0xB4 */ 132 unsigned int wkup_i2c0ctrl; /* offset 0xB8 */ 133 unsigned int wkup_adctscctrl; /* offset 0xBC */ 134 unsigned int resv12; 135 unsigned int timer1clkctrl; /* offset 0xC4 */ 136 unsigned int resv13[4]; 137 unsigned int divm6dpllcore; /* offset 0xD8 */ 138 }; 139 140 /** 141 * Encapsulating peripheral functional clocks 142 * pll registers 143 */ 144 struct cm_perpll { 145 unsigned int l4lsclkstctrl; /* offset 0x00 */ 146 unsigned int l3sclkstctrl; /* offset 0x04 */ 147 unsigned int l4fwclkstctrl; /* offset 0x08 */ 148 unsigned int l3clkstctrl; /* offset 0x0c */ 149 unsigned int resv1; 150 unsigned int cpgmac0clkctrl; /* offset 0x14 */ 151 unsigned int lcdclkctrl; /* offset 0x18 */ 152 unsigned int usb0clkctrl; /* offset 0x1C */ 153 unsigned int resv2; 154 unsigned int tptc0clkctrl; /* offset 0x24 */ 155 unsigned int emifclkctrl; /* offset 0x28 */ 156 unsigned int ocmcramclkctrl; /* offset 0x2c */ 157 unsigned int gpmcclkctrl; /* offset 0x30 */ 158 unsigned int mcasp0clkctrl; /* offset 0x34 */ 159 unsigned int uart5clkctrl; /* offset 0x38 */ 160 unsigned int mmc0clkctrl; /* offset 0x3C */ 161 unsigned int elmclkctrl; /* offset 0x40 */ 162 unsigned int i2c2clkctrl; /* offset 0x44 */ 163 unsigned int i2c1clkctrl; /* offset 0x48 */ 164 unsigned int spi0clkctrl; /* offset 0x4C */ 165 unsigned int spi1clkctrl; /* offset 0x50 */ 166 unsigned int resv3[3]; 167 unsigned int l4lsclkctrl; /* offset 0x60 */ 168 unsigned int l4fwclkctrl; /* offset 0x64 */ 169 unsigned int mcasp1clkctrl; /* offset 0x68 */ 170 unsigned int uart1clkctrl; /* offset 0x6C */ 171 unsigned int uart2clkctrl; /* offset 0x70 */ 172 unsigned int uart3clkctrl; /* offset 0x74 */ 173 unsigned int uart4clkctrl; /* offset 0x78 */ 174 unsigned int timer7clkctrl; /* offset 0x7C */ 175 unsigned int timer2clkctrl; /* offset 0x80 */ 176 unsigned int timer3clkctrl; /* offset 0x84 */ 177 unsigned int timer4clkctrl; /* offset 0x88 */ 178 unsigned int resv4[8]; 179 unsigned int gpio1clkctrl; /* offset 0xAC */ 180 unsigned int gpio2clkctrl; /* offset 0xB0 */ 181 unsigned int gpio3clkctrl; /* offset 0xB4 */ 182 unsigned int resv5; 183 unsigned int tpccclkctrl; /* offset 0xBC */ 184 unsigned int dcan0clkctrl; /* offset 0xC0 */ 185 unsigned int dcan1clkctrl; /* offset 0xC4 */ 186 unsigned int resv6; 187 unsigned int epwmss1clkctrl; /* offset 0xCC */ 188 unsigned int emiffwclkctrl; /* offset 0xD0 */ 189 unsigned int epwmss0clkctrl; /* offset 0xD4 */ 190 unsigned int epwmss2clkctrl; /* offset 0xD8 */ 191 unsigned int l3instrclkctrl; /* offset 0xDC */ 192 unsigned int l3clkctrl; /* Offset 0xE0 */ 193 unsigned int resv8[2]; 194 unsigned int timer5clkctrl; /* offset 0xEC */ 195 unsigned int timer6clkctrl; /* offset 0xF0 */ 196 unsigned int mmc1clkctrl; /* offset 0xF4 */ 197 unsigned int mmc2clkctrl; /* offset 0xF8 */ 198 unsigned int resv9[8]; 199 unsigned int l4hsclkstctrl; /* offset 0x11C */ 200 unsigned int l4hsclkctrl; /* offset 0x120 */ 201 unsigned int resv10[8]; 202 unsigned int cpswclkstctrl; /* offset 0x144 */ 203 unsigned int lcdcclkstctrl; /* offset 0x148 */ 204 }; 205 206 /* Encapsulating Display pll registers */ 207 struct cm_dpll { 208 unsigned int resv1; 209 unsigned int clktimer7clk; /* offset 0x04 */ 210 unsigned int clktimer2clk; /* offset 0x08 */ 211 unsigned int clktimer3clk; /* offset 0x0C */ 212 unsigned int clktimer4clk; /* offset 0x10 */ 213 unsigned int resv2; 214 unsigned int clktimer5clk; /* offset 0x18 */ 215 unsigned int clktimer6clk; /* offset 0x1C */ 216 unsigned int resv3[2]; 217 unsigned int clktimer1clk; /* offset 0x28 */ 218 unsigned int resv4[2]; 219 unsigned int clklcdcpixelclk; /* offset 0x34 */ 220 }; 221 222 struct prm_device_inst { 223 unsigned int prm_rstctrl; 224 unsigned int prm_rsttime; 225 unsigned int prm_rstst; 226 }; 227 #else 228 /* Encapsulating core pll registers */ 229 struct cm_wkuppll { 230 unsigned int resv0[136]; 231 unsigned int wkl4wkclkctrl; /* offset 0x220 */ 232 unsigned int resv1[7]; 233 unsigned int usbphy0clkctrl; /* offset 0x240 */ 234 unsigned int resv112; 235 unsigned int usbphy1clkctrl; /* offset 0x248 */ 236 unsigned int resv113[45]; 237 unsigned int wkclkstctrl; /* offset 0x300 */ 238 unsigned int resv2[15]; 239 unsigned int wkup_i2c0ctrl; /* offset 0x340 */ 240 unsigned int resv3; 241 unsigned int wkup_uart0ctrl; /* offset 0x348 */ 242 unsigned int resv4[5]; 243 unsigned int wkctrlclkctrl; /* offset 0x360 */ 244 unsigned int resv5; 245 unsigned int wkgpio0clkctrl; /* offset 0x368 */ 246 247 unsigned int resv6[109]; 248 unsigned int clkmoddpllcore; /* offset 0x520 */ 249 unsigned int idlestdpllcore; /* offset 0x524 */ 250 unsigned int resv61; 251 unsigned int clkseldpllcore; /* offset 0x52C */ 252 unsigned int resv7[2]; 253 unsigned int divm4dpllcore; /* offset 0x538 */ 254 unsigned int divm5dpllcore; /* offset 0x53C */ 255 unsigned int divm6dpllcore; /* offset 0x540 */ 256 257 unsigned int resv8[7]; 258 unsigned int clkmoddpllmpu; /* offset 0x560 */ 259 unsigned int idlestdpllmpu; /* offset 0x564 */ 260 unsigned int resv9; 261 unsigned int clkseldpllmpu; /* offset 0x56c */ 262 unsigned int divm2dpllmpu; /* offset 0x570 */ 263 264 unsigned int resv10[11]; 265 unsigned int clkmoddpllddr; /* offset 0x5A0 */ 266 unsigned int idlestdpllddr; /* offset 0x5A4 */ 267 unsigned int resv11; 268 unsigned int clkseldpllddr; /* offset 0x5AC */ 269 unsigned int divm2dpllddr; /* offset 0x5B0 */ 270 271 unsigned int resv12[11]; 272 unsigned int clkmoddpllper; /* offset 0x5E0 */ 273 unsigned int idlestdpllper; /* offset 0x5E4 */ 274 unsigned int resv13; 275 unsigned int clkseldpllper; /* offset 0x5EC */ 276 unsigned int divm2dpllper; /* offset 0x5F0 */ 277 unsigned int resv14[8]; 278 unsigned int clkdcoldodpllper; /* offset 0x614 */ 279 280 unsigned int resv15[2]; 281 unsigned int clkmoddplldisp; /* offset 0x620 */ 282 unsigned int resv16[2]; 283 unsigned int clkseldplldisp; /* offset 0x62C */ 284 unsigned int divm2dplldisp; /* offset 0x630 */ 285 }; 286 287 /* 288 * Encapsulating peripheral functional clocks 289 * pll registers 290 */ 291 struct cm_perpll { 292 unsigned int l3clkstctrl; /* offset 0x00 */ 293 unsigned int resv0[7]; 294 unsigned int l3clkctrl; /* Offset 0x20 */ 295 unsigned int resv112[7]; 296 unsigned int l3instrclkctrl; /* offset 0x40 */ 297 unsigned int resv2[3]; 298 unsigned int ocmcramclkctrl; /* offset 0x50 */ 299 unsigned int resv3[9]; 300 unsigned int tpccclkctrl; /* offset 0x78 */ 301 unsigned int resv4; 302 unsigned int tptc0clkctrl; /* offset 0x80 */ 303 304 unsigned int resv5[7]; 305 unsigned int l4hsclkctrl; /* offset 0x0A0 */ 306 unsigned int resv6; 307 unsigned int l4fwclkctrl; /* offset 0x0A8 */ 308 unsigned int resv7[85]; 309 unsigned int l3sclkstctrl; /* offset 0x200 */ 310 unsigned int resv8[7]; 311 unsigned int gpmcclkctrl; /* offset 0x220 */ 312 unsigned int resv9[5]; 313 unsigned int mcasp0clkctrl; /* offset 0x238 */ 314 unsigned int resv10; 315 unsigned int mcasp1clkctrl; /* offset 0x240 */ 316 unsigned int resv11; 317 unsigned int mmc2clkctrl; /* offset 0x248 */ 318 unsigned int resv12[3]; 319 unsigned int qspiclkctrl; /* offset 0x258 */ 320 unsigned int resv121; 321 unsigned int usb0clkctrl; /* offset 0x260 */ 322 unsigned int resv122; 323 unsigned int usb1clkctrl; /* offset 0x268 */ 324 unsigned int resv13[101]; 325 unsigned int l4lsclkstctrl; /* offset 0x400 */ 326 unsigned int resv14[7]; 327 unsigned int l4lsclkctrl; /* offset 0x420 */ 328 unsigned int resv15; 329 unsigned int dcan0clkctrl; /* offset 0x428 */ 330 unsigned int resv16; 331 unsigned int dcan1clkctrl; /* offset 0x430 */ 332 unsigned int resv17[13]; 333 unsigned int elmclkctrl; /* offset 0x468 */ 334 335 unsigned int resv18[3]; 336 unsigned int gpio1clkctrl; /* offset 0x478 */ 337 unsigned int resv19; 338 unsigned int gpio2clkctrl; /* offset 0x480 */ 339 unsigned int resv20; 340 unsigned int gpio3clkctrl; /* offset 0x488 */ 341 unsigned int resv41; 342 unsigned int gpio4clkctrl; /* offset 0x490 */ 343 unsigned int resv42; 344 unsigned int gpio5clkctrl; /* offset 0x498 */ 345 unsigned int resv21[3]; 346 347 unsigned int i2c1clkctrl; /* offset 0x4A8 */ 348 unsigned int resv22; 349 unsigned int i2c2clkctrl; /* offset 0x4B0 */ 350 unsigned int resv23[3]; 351 unsigned int mmc0clkctrl; /* offset 0x4C0 */ 352 unsigned int resv24; 353 unsigned int mmc1clkctrl; /* offset 0x4C8 */ 354 355 unsigned int resv25[13]; 356 unsigned int spi0clkctrl; /* offset 0x500 */ 357 unsigned int resv26; 358 unsigned int spi1clkctrl; /* offset 0x508 */ 359 unsigned int resv27[9]; 360 unsigned int timer2clkctrl; /* offset 0x530 */ 361 unsigned int resv28; 362 unsigned int timer3clkctrl; /* offset 0x538 */ 363 unsigned int resv29; 364 unsigned int timer4clkctrl; /* offset 0x540 */ 365 unsigned int resv30[5]; 366 unsigned int timer7clkctrl; /* offset 0x558 */ 367 368 unsigned int resv31[9]; 369 unsigned int uart1clkctrl; /* offset 0x580 */ 370 unsigned int resv32; 371 unsigned int uart2clkctrl; /* offset 0x588 */ 372 unsigned int resv33; 373 unsigned int uart3clkctrl; /* offset 0x590 */ 374 unsigned int resv34; 375 unsigned int uart4clkctrl; /* offset 0x598 */ 376 unsigned int resv35; 377 unsigned int uart5clkctrl; /* offset 0x5A0 */ 378 unsigned int resv36[5]; 379 unsigned int usbphyocp2scp0clkctrl; /* offset 0x5B8 */ 380 unsigned int resv361; 381 unsigned int usbphyocp2scp1clkctrl; /* offset 0x5C0 */ 382 unsigned int resv3611[79]; 383 384 unsigned int emifclkstctrl; /* offset 0x700 */ 385 unsigned int resv362[7]; 386 unsigned int emifclkctrl; /* offset 0x720 */ 387 unsigned int resv37[3]; 388 unsigned int emiffwclkctrl; /* offset 0x730 */ 389 unsigned int resv371; 390 unsigned int otfaemifclkctrl; /* offset 0x738 */ 391 unsigned int resv38[57]; 392 unsigned int lcdclkctrl; /* offset 0x820 */ 393 unsigned int resv39[183]; 394 unsigned int cpswclkstctrl; /* offset 0xB00 */ 395 unsigned int resv40[7]; 396 unsigned int cpgmac0clkctrl; /* offset 0xB20 */ 397 }; 398 399 struct cm_device_inst { 400 unsigned int cm_clkout1_ctrl; 401 unsigned int cm_dll_ctrl; 402 }; 403 404 struct prm_device_inst { 405 unsigned int prm_rstctrl; 406 unsigned int prm_rstst; 407 }; 408 409 struct cm_dpll { 410 unsigned int resv1; 411 unsigned int clktimer2clk; /* offset 0x04 */ 412 unsigned int resv2[11]; 413 unsigned int clkselmacclk; /* offset 0x34 */ 414 }; 415 #endif /* CONFIG_AM43XX */ 416 417 /* Control Module RTC registers */ 418 struct cm_rtc { 419 unsigned int rtcclkctrl; /* offset 0x0 */ 420 unsigned int clkstctrl; /* offset 0x4 */ 421 }; 422 423 /* Watchdog timer registers */ 424 struct wd_timer { 425 unsigned int resv1[4]; 426 unsigned int wdtwdsc; /* offset 0x010 */ 427 unsigned int wdtwdst; /* offset 0x014 */ 428 unsigned int wdtwisr; /* offset 0x018 */ 429 unsigned int wdtwier; /* offset 0x01C */ 430 unsigned int wdtwwer; /* offset 0x020 */ 431 unsigned int wdtwclr; /* offset 0x024 */ 432 unsigned int wdtwcrr; /* offset 0x028 */ 433 unsigned int wdtwldr; /* offset 0x02C */ 434 unsigned int wdtwtgr; /* offset 0x030 */ 435 unsigned int wdtwwps; /* offset 0x034 */ 436 unsigned int resv2[3]; 437 unsigned int wdtwdly; /* offset 0x044 */ 438 unsigned int wdtwspr; /* offset 0x048 */ 439 unsigned int resv3[1]; 440 unsigned int wdtwqeoi; /* offset 0x050 */ 441 unsigned int wdtwqstar; /* offset 0x054 */ 442 unsigned int wdtwqsta; /* offset 0x058 */ 443 unsigned int wdtwqens; /* offset 0x05C */ 444 unsigned int wdtwqenc; /* offset 0x060 */ 445 unsigned int resv4[39]; 446 unsigned int wdt_unfr; /* offset 0x100 */ 447 }; 448 449 /* Timer 32 bit registers */ 450 struct gptimer { 451 unsigned int tidr; /* offset 0x00 */ 452 unsigned char res1[12]; 453 unsigned int tiocp_cfg; /* offset 0x10 */ 454 unsigned char res2[12]; 455 unsigned int tier; /* offset 0x20 */ 456 unsigned int tistatr; /* offset 0x24 */ 457 unsigned int tistat; /* offset 0x28 */ 458 unsigned int tisr; /* offset 0x2c */ 459 unsigned int tcicr; /* offset 0x30 */ 460 unsigned int twer; /* offset 0x34 */ 461 unsigned int tclr; /* offset 0x38 */ 462 unsigned int tcrr; /* offset 0x3c */ 463 unsigned int tldr; /* offset 0x40 */ 464 unsigned int ttgr; /* offset 0x44 */ 465 unsigned int twpc; /* offset 0x48 */ 466 unsigned int tmar; /* offset 0x4c */ 467 unsigned int tcar1; /* offset 0x50 */ 468 unsigned int tscir; /* offset 0x54 */ 469 unsigned int tcar2; /* offset 0x58 */ 470 }; 471 472 /* UART Registers */ 473 struct uart_sys { 474 unsigned int resv1[21]; 475 unsigned int uartsyscfg; /* offset 0x54 */ 476 unsigned int uartsyssts; /* offset 0x58 */ 477 }; 478 479 /* VTP Registers */ 480 struct vtp_reg { 481 unsigned int vtp0ctrlreg; 482 }; 483 484 /* Control Status Register */ 485 struct ctrl_stat { 486 unsigned int resv1[16]; 487 unsigned int statusreg; /* ofset 0x40 */ 488 unsigned int resv2[51]; 489 unsigned int secure_emif_sdram_config; /* offset 0x0110 */ 490 unsigned int resv3[319]; 491 unsigned int dev_attr; 492 }; 493 494 /* AM33XX GPIO registers */ 495 #define OMAP_GPIO_REVISION 0x0000 496 #define OMAP_GPIO_SYSCONFIG 0x0010 497 #define OMAP_GPIO_SYSSTATUS 0x0114 498 #define OMAP_GPIO_IRQSTATUS1 0x002c 499 #define OMAP_GPIO_IRQSTATUS2 0x0030 500 #define OMAP_GPIO_CTRL 0x0130 501 #define OMAP_GPIO_OE 0x0134 502 #define OMAP_GPIO_DATAIN 0x0138 503 #define OMAP_GPIO_DATAOUT 0x013c 504 #define OMAP_GPIO_LEVELDETECT0 0x0140 505 #define OMAP_GPIO_LEVELDETECT1 0x0144 506 #define OMAP_GPIO_RISINGDETECT 0x0148 507 #define OMAP_GPIO_FALLINGDETECT 0x014c 508 #define OMAP_GPIO_DEBOUNCE_EN 0x0150 509 #define OMAP_GPIO_DEBOUNCE_VAL 0x0154 510 #define OMAP_GPIO_CLEARDATAOUT 0x0190 511 #define OMAP_GPIO_SETDATAOUT 0x0194 512 513 /* Control Device Register */ 514 515 /* Control Device Register */ 516 #define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F 517 #define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8 518 #define MREQPRIO_1_DSS_MASK 0xFFFFFF8F 519 520 struct ctrl_dev { 521 unsigned int deviceid; /* offset 0x00 */ 522 unsigned int resv1[7]; 523 unsigned int usb_ctrl0; /* offset 0x20 */ 524 unsigned int resv2; 525 unsigned int usb_ctrl1; /* offset 0x28 */ 526 unsigned int resv3; 527 unsigned int macid0l; /* offset 0x30 */ 528 unsigned int macid0h; /* offset 0x34 */ 529 unsigned int macid1l; /* offset 0x38 */ 530 unsigned int macid1h; /* offset 0x3c */ 531 unsigned int resv4[4]; 532 unsigned int miisel; /* offset 0x50 */ 533 unsigned int resv5[7]; 534 unsigned int mreqprio_0; /* offset 0x70 */ 535 unsigned int mreqprio_1; /* offset 0x74 */ 536 unsigned int resv6[97]; 537 unsigned int efuse_sma; /* offset 0x1FC */ 538 }; 539 540 /* Bandwidth Limiter Portion of the L3Fast Configuration Register */ 541 #define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0 542 #define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0 543 #define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800 544 545 struct l3f_cfg_bwlimiter { 546 u32 padding0[2]; 547 u32 modena_init0_bw_fractional; 548 u32 modena_init0_bw_integer; 549 u32 modena_init0_watermark_0; 550 }; 551 552 /* gmii_sel register defines */ 553 #define GMII1_SEL_MII 0x0 554 #define GMII1_SEL_RMII 0x1 555 #define GMII1_SEL_RGMII 0x2 556 #define GMII2_SEL_MII 0x0 557 #define GMII2_SEL_RMII 0x4 558 #define GMII2_SEL_RGMII 0x8 559 #define RGMII1_IDMODE BIT(4) 560 #define RGMII2_IDMODE BIT(5) 561 #define RMII1_IO_CLK_EN BIT(6) 562 #define RMII2_IO_CLK_EN BIT(7) 563 564 #define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII) 565 #define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII) 566 #define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII) 567 #define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE) 568 #define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN) 569 570 /* PWMSS */ 571 struct pwmss_regs { 572 unsigned int idver; 573 unsigned int sysconfig; 574 unsigned int clkconfig; 575 unsigned int clkstatus; 576 }; 577 #define ECAP_CLK_EN BIT(0) 578 #define ECAP_CLK_STOP_REQ BIT(1) 579 580 struct pwmss_ecap_regs { 581 unsigned int tsctr; 582 unsigned int ctrphs; 583 unsigned int cap1; 584 unsigned int cap2; 585 unsigned int cap3; 586 unsigned int cap4; 587 unsigned int resv1[4]; 588 unsigned short ecctl1; 589 unsigned short ecctl2; 590 }; 591 592 /* Capture Control register 2 */ 593 #define ECTRL2_SYNCOSEL_MASK (0x03 << 6) 594 #define ECTRL2_MDSL_ECAP BIT(9) 595 #define ECTRL2_CTRSTP_FREERUN BIT(4) 596 #define ECTRL2_PLSL_LOW BIT(10) 597 #define ECTRL2_SYNC_EN BIT(5) 598 599 #endif /* __ASSEMBLY__ */ 600 #endif /* __KERNEL_STRICT_NAMES */ 601 602 #endif /* _AM33XX_CPU_H */ 603