1 /* 2 * cpu.h 3 * 4 * AM33xx specific header file 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef _AM33XX_CPU_H 20 #define _AM33XX_CPU_H 21 22 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 23 #include <asm/types.h> 24 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 25 26 #include <asm/arch/hardware.h> 27 28 #define BIT(x) (1 << x) 29 #define CL_BIT(x) (0 << x) 30 31 /* Timer register bits */ 32 #define TCLR_ST BIT(0) /* Start=1 Stop=0 */ 33 #define TCLR_AR BIT(1) /* Auto reload */ 34 #define TCLR_PRE BIT(5) /* Pre-scaler enable */ 35 #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */ 36 #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */ 37 38 /* device type */ 39 #define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) 40 #define TST_DEVICE 0x0 41 #define EMU_DEVICE 0x1 42 #define HS_DEVICE 0x2 43 #define GP_DEVICE 0x3 44 45 /* cpu-id for AM33XX family */ 46 #define AM335X 0xB944 47 #define DEVICE_ID 0x44E10600 48 49 /* This gives the status of the boot mode pins on the evm */ 50 #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ 51 | BIT(3) | BIT(4)) 52 53 /* Reset control */ 54 #ifdef CONFIG_AM33XX 55 #define PRM_RSTCTRL 0x44E00F00 56 #define PRM_RSTST 0x44E00F08 57 #endif 58 #define PRM_RSTCTRL_RESET 0x01 59 #define PRM_RSTST_WARM_RESET_MASK 0x232 60 61 #ifndef __KERNEL_STRICT_NAMES 62 #ifndef __ASSEMBLY__ 63 struct gpmc_cs { 64 u32 config1; /* 0x00 */ 65 u32 config2; /* 0x04 */ 66 u32 config3; /* 0x08 */ 67 u32 config4; /* 0x0C */ 68 u32 config5; /* 0x10 */ 69 u32 config6; /* 0x14 */ 70 u32 config7; /* 0x18 */ 71 u32 nand_cmd; /* 0x1C */ 72 u32 nand_adr; /* 0x20 */ 73 u32 nand_dat; /* 0x24 */ 74 u8 res[8]; /* blow up to 0x30 byte */ 75 }; 76 77 struct bch_res_0_3 { 78 u32 bch_result_x[4]; 79 }; 80 81 struct gpmc { 82 u8 res1[0x10]; 83 u32 sysconfig; /* 0x10 */ 84 u8 res2[0x4]; 85 u32 irqstatus; /* 0x18 */ 86 u32 irqenable; /* 0x1C */ 87 u8 res3[0x20]; 88 u32 timeout_control; /* 0x40 */ 89 u8 res4[0xC]; 90 u32 config; /* 0x50 */ 91 u32 status; /* 0x54 */ 92 u8 res5[0x8]; /* 0x58 */ 93 struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ 94 u8 res6[0x14]; /* 0x1E0 */ 95 u32 ecc_config; /* 0x1F4 */ 96 u32 ecc_control; /* 0x1F8 */ 97 u32 ecc_size_config; /* 0x1FC */ 98 u32 ecc1_result; /* 0x200 */ 99 u32 ecc2_result; /* 0x204 */ 100 u32 ecc3_result; /* 0x208 */ 101 u32 ecc4_result; /* 0x20C */ 102 u32 ecc5_result; /* 0x210 */ 103 u32 ecc6_result; /* 0x214 */ 104 u32 ecc7_result; /* 0x218 */ 105 u32 ecc8_result; /* 0x21C */ 106 u32 ecc9_result; /* 0x220 */ 107 u8 res7[12]; /* 0x224 */ 108 u32 testmomde_ctrl; /* 0x230 */ 109 u8 res8[12]; /* 0x234 */ 110 struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */ 111 }; 112 113 /* Used for board specific gpmc initialization */ 114 extern struct gpmc *gpmc_cfg; 115 116 /* Encapsulating core pll registers */ 117 struct cm_wkuppll { 118 unsigned int wkclkstctrl; /* offset 0x00 */ 119 unsigned int wkctrlclkctrl; /* offset 0x04 */ 120 unsigned int wkgpio0clkctrl; /* offset 0x08 */ 121 unsigned int wkl4wkclkctrl; /* offset 0x0c */ 122 unsigned int resv2[4]; 123 unsigned int idlestdpllmpu; /* offset 0x20 */ 124 unsigned int resv3[2]; 125 unsigned int clkseldpllmpu; /* offset 0x2c */ 126 unsigned int resv4[1]; 127 unsigned int idlestdpllddr; /* offset 0x34 */ 128 unsigned int resv5[2]; 129 unsigned int clkseldpllddr; /* offset 0x40 */ 130 unsigned int resv6[4]; 131 unsigned int clkseldplldisp; /* offset 0x54 */ 132 unsigned int resv7[1]; 133 unsigned int idlestdpllcore; /* offset 0x5c */ 134 unsigned int resv8[2]; 135 unsigned int clkseldpllcore; /* offset 0x68 */ 136 unsigned int resv9[1]; 137 unsigned int idlestdpllper; /* offset 0x70 */ 138 unsigned int resv10[2]; 139 unsigned int clkdcoldodpllper; /* offset 0x7c */ 140 unsigned int divm4dpllcore; /* offset 0x80 */ 141 unsigned int divm5dpllcore; /* offset 0x84 */ 142 unsigned int clkmoddpllmpu; /* offset 0x88 */ 143 unsigned int clkmoddpllper; /* offset 0x8c */ 144 unsigned int clkmoddpllcore; /* offset 0x90 */ 145 unsigned int clkmoddpllddr; /* offset 0x94 */ 146 unsigned int clkmoddplldisp; /* offset 0x98 */ 147 unsigned int clkseldpllper; /* offset 0x9c */ 148 unsigned int divm2dpllddr; /* offset 0xA0 */ 149 unsigned int divm2dplldisp; /* offset 0xA4 */ 150 unsigned int divm2dpllmpu; /* offset 0xA8 */ 151 unsigned int divm2dpllper; /* offset 0xAC */ 152 unsigned int resv11[1]; 153 unsigned int wkup_uart0ctrl; /* offset 0xB4 */ 154 unsigned int wkup_i2c0ctrl; /* offset 0xB8 */ 155 unsigned int resv12[7]; 156 unsigned int divm6dpllcore; /* offset 0xD8 */ 157 }; 158 159 /** 160 * Encapsulating peripheral functional clocks 161 * pll registers 162 */ 163 struct cm_perpll { 164 unsigned int l4lsclkstctrl; /* offset 0x00 */ 165 unsigned int l3sclkstctrl; /* offset 0x04 */ 166 unsigned int l4fwclkstctrl; /* offset 0x08 */ 167 unsigned int l3clkstctrl; /* offset 0x0c */ 168 unsigned int resv1; 169 unsigned int cpgmac0clkctrl; /* offset 0x14 */ 170 unsigned int lcdclkctrl; /* offset 0x18 */ 171 unsigned int usb0clkctrl; /* offset 0x1C */ 172 unsigned int resv2; 173 unsigned int tptc0clkctrl; /* offset 0x24 */ 174 unsigned int emifclkctrl; /* offset 0x28 */ 175 unsigned int ocmcramclkctrl; /* offset 0x2c */ 176 unsigned int gpmcclkctrl; /* offset 0x30 */ 177 unsigned int mcasp0clkctrl; /* offset 0x34 */ 178 unsigned int uart5clkctrl; /* offset 0x38 */ 179 unsigned int mmc0clkctrl; /* offset 0x3C */ 180 unsigned int elmclkctrl; /* offset 0x40 */ 181 unsigned int i2c2clkctrl; /* offset 0x44 */ 182 unsigned int i2c1clkctrl; /* offset 0x48 */ 183 unsigned int spi0clkctrl; /* offset 0x4C */ 184 unsigned int spi1clkctrl; /* offset 0x50 */ 185 unsigned int resv3[3]; 186 unsigned int l4lsclkctrl; /* offset 0x60 */ 187 unsigned int l4fwclkctrl; /* offset 0x64 */ 188 unsigned int mcasp1clkctrl; /* offset 0x68 */ 189 unsigned int uart1clkctrl; /* offset 0x6C */ 190 unsigned int uart2clkctrl; /* offset 0x70 */ 191 unsigned int uart3clkctrl; /* offset 0x74 */ 192 unsigned int uart4clkctrl; /* offset 0x78 */ 193 unsigned int timer7clkctrl; /* offset 0x7C */ 194 unsigned int timer2clkctrl; /* offset 0x80 */ 195 unsigned int timer3clkctrl; /* offset 0x84 */ 196 unsigned int timer4clkctrl; /* offset 0x88 */ 197 unsigned int resv4[8]; 198 unsigned int gpio1clkctrl; /* offset 0xAC */ 199 unsigned int gpio2clkctrl; /* offset 0xB0 */ 200 unsigned int gpio3clkctrl; /* offset 0xB4 */ 201 unsigned int resv5; 202 unsigned int tpccclkctrl; /* offset 0xBC */ 203 unsigned int dcan0clkctrl; /* offset 0xC0 */ 204 unsigned int dcan1clkctrl; /* offset 0xC4 */ 205 unsigned int resv6[2]; 206 unsigned int emiffwclkctrl; /* offset 0xD0 */ 207 unsigned int resv7[2]; 208 unsigned int l3instrclkctrl; /* offset 0xDC */ 209 unsigned int l3clkctrl; /* Offset 0xE0 */ 210 unsigned int resv8[4]; 211 unsigned int mmc1clkctrl; /* offset 0xF4 */ 212 unsigned int mmc2clkctrl; /* offset 0xF8 */ 213 unsigned int resv9[8]; 214 unsigned int l4hsclkstctrl; /* offset 0x11C */ 215 unsigned int l4hsclkctrl; /* offset 0x120 */ 216 unsigned int resv10[8]; 217 unsigned int cpswclkstctrl; /* offset 0x144 */ 218 }; 219 220 /* Encapsulating Display pll registers */ 221 struct cm_dpll { 222 unsigned int resv1[2]; 223 unsigned int clktimer2clk; /* offset 0x08 */ 224 }; 225 226 /* Control Module RTC registers */ 227 struct cm_rtc { 228 unsigned int rtcclkctrl; /* offset 0x0 */ 229 unsigned int clkstctrl; /* offset 0x4 */ 230 }; 231 232 /* Watchdog timer registers */ 233 struct wd_timer { 234 unsigned int resv1[4]; 235 unsigned int wdtwdsc; /* offset 0x010 */ 236 unsigned int wdtwdst; /* offset 0x014 */ 237 unsigned int wdtwisr; /* offset 0x018 */ 238 unsigned int wdtwier; /* offset 0x01C */ 239 unsigned int wdtwwer; /* offset 0x020 */ 240 unsigned int wdtwclr; /* offset 0x024 */ 241 unsigned int wdtwcrr; /* offset 0x028 */ 242 unsigned int wdtwldr; /* offset 0x02C */ 243 unsigned int wdtwtgr; /* offset 0x030 */ 244 unsigned int wdtwwps; /* offset 0x034 */ 245 unsigned int resv2[3]; 246 unsigned int wdtwdly; /* offset 0x044 */ 247 unsigned int wdtwspr; /* offset 0x048 */ 248 unsigned int resv3[1]; 249 unsigned int wdtwqeoi; /* offset 0x050 */ 250 unsigned int wdtwqstar; /* offset 0x054 */ 251 unsigned int wdtwqsta; /* offset 0x058 */ 252 unsigned int wdtwqens; /* offset 0x05C */ 253 unsigned int wdtwqenc; /* offset 0x060 */ 254 unsigned int resv4[39]; 255 unsigned int wdt_unfr; /* offset 0x100 */ 256 }; 257 258 /* Timer 32 bit registers */ 259 struct gptimer { 260 unsigned int tidr; /* offset 0x00 */ 261 unsigned char res1[12]; 262 unsigned int tiocp_cfg; /* offset 0x10 */ 263 unsigned char res2[12]; 264 unsigned int tier; /* offset 0x20 */ 265 unsigned int tistatr; /* offset 0x24 */ 266 unsigned int tistat; /* offset 0x28 */ 267 unsigned int tisr; /* offset 0x2c */ 268 unsigned int tcicr; /* offset 0x30 */ 269 unsigned int twer; /* offset 0x34 */ 270 unsigned int tclr; /* offset 0x38 */ 271 unsigned int tcrr; /* offset 0x3c */ 272 unsigned int tldr; /* offset 0x40 */ 273 unsigned int ttgr; /* offset 0x44 */ 274 unsigned int twpc; /* offset 0x48 */ 275 unsigned int tmar; /* offset 0x4c */ 276 unsigned int tcar1; /* offset 0x50 */ 277 unsigned int tscir; /* offset 0x54 */ 278 unsigned int tcar2; /* offset 0x58 */ 279 }; 280 281 /* RTC Registers */ 282 struct rtc_regs { 283 unsigned int res[21]; 284 unsigned int osc; /* offset 0x54 */ 285 unsigned int res2[5]; 286 unsigned int kick0r; /* offset 0x6c */ 287 unsigned int kick1r; /* offset 0x70 */ 288 }; 289 290 /* UART Registers */ 291 struct uart_sys { 292 unsigned int resv1[21]; 293 unsigned int uartsyscfg; /* offset 0x54 */ 294 unsigned int uartsyssts; /* offset 0x58 */ 295 }; 296 297 /* VTP Registers */ 298 struct vtp_reg { 299 unsigned int vtp0ctrlreg; 300 }; 301 302 /* Control Status Register */ 303 struct ctrl_stat { 304 unsigned int resv1[16]; 305 unsigned int statusreg; /* ofset 0x40 */ 306 unsigned int resv2[51]; 307 unsigned int secure_emif_sdram_config; /* offset 0x0110 */ 308 }; 309 310 /* AM33XX GPIO registers */ 311 #define OMAP_GPIO_REVISION 0x0000 312 #define OMAP_GPIO_SYSCONFIG 0x0010 313 #define OMAP_GPIO_SYSSTATUS 0x0114 314 #define OMAP_GPIO_IRQSTATUS1 0x002c 315 #define OMAP_GPIO_IRQSTATUS2 0x0030 316 #define OMAP_GPIO_CTRL 0x0130 317 #define OMAP_GPIO_OE 0x0134 318 #define OMAP_GPIO_DATAIN 0x0138 319 #define OMAP_GPIO_DATAOUT 0x013c 320 #define OMAP_GPIO_LEVELDETECT0 0x0140 321 #define OMAP_GPIO_LEVELDETECT1 0x0144 322 #define OMAP_GPIO_RISINGDETECT 0x0148 323 #define OMAP_GPIO_FALLINGDETECT 0x014c 324 #define OMAP_GPIO_DEBOUNCE_EN 0x0150 325 #define OMAP_GPIO_DEBOUNCE_VAL 0x0154 326 #define OMAP_GPIO_CLEARDATAOUT 0x0190 327 #define OMAP_GPIO_SETDATAOUT 0x0194 328 329 /* Control Device Register */ 330 struct ctrl_dev { 331 unsigned int deviceid; /* offset 0x00 */ 332 unsigned int resv1[7]; 333 unsigned int usb_ctrl0; /* offset 0x20 */ 334 unsigned int resv2; 335 unsigned int usb_ctrl1; /* offset 0x28 */ 336 unsigned int resv3; 337 unsigned int macid0l; /* offset 0x30 */ 338 unsigned int macid0h; /* offset 0x34 */ 339 unsigned int macid1l; /* offset 0x38 */ 340 unsigned int macid1h; /* offset 0x3c */ 341 unsigned int resv4[4]; 342 unsigned int miisel; /* offset 0x50 */ 343 }; 344 #endif /* __ASSEMBLY__ */ 345 #endif /* __KERNEL_STRICT_NAMES */ 346 347 #endif /* _AM33XX_CPU_H */ 348