1 /* 2 * cpu.h 3 * 4 * AM33xx specific header file 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _AM33XX_CPU_H 12 #define _AM33XX_CPU_H 13 14 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 15 #include <asm/types.h> 16 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 17 18 #include <asm/arch/hardware.h> 19 20 #define BIT(x) (1 << x) 21 #define CL_BIT(x) (0 << x) 22 23 /* Timer register bits */ 24 #define TCLR_ST BIT(0) /* Start=1 Stop=0 */ 25 #define TCLR_AR BIT(1) /* Auto reload */ 26 #define TCLR_PRE BIT(5) /* Pre-scaler enable */ 27 #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */ 28 #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */ 29 30 /* device type */ 31 #define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) 32 #define TST_DEVICE 0x0 33 #define EMU_DEVICE 0x1 34 #define HS_DEVICE 0x2 35 #define GP_DEVICE 0x3 36 37 /* cpu-id for AM33XX and TI81XX family */ 38 #define AM335X 0xB944 39 #define TI81XX 0xB81E 40 #define DEVICE_ID (CTRL_BASE + 0x0600) 41 42 /* This gives the status of the boot mode pins on the evm */ 43 #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ 44 | BIT(3) | BIT(4)) 45 46 #define PRM_RSTCTRL_RESET 0x01 47 #define PRM_RSTST_WARM_RESET_MASK 0x232 48 49 /* 50 * Watchdog: 51 * Using the prescaler, the OMAP watchdog could go for many 52 * months before firing. These limits work without scaling, 53 * with the 60 second default assumed by most tools and docs. 54 */ 55 #define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */ 56 #define TIMER_MARGIN_DEFAULT 60 /* 60 secs */ 57 #define TIMER_MARGIN_MIN 1 58 59 #define PTV 0 /* prescale */ 60 #define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1) 61 #define WDT_WWPS_PEND_WCLR BIT(0) 62 #define WDT_WWPS_PEND_WLDR BIT(2) 63 #define WDT_WWPS_PEND_WTGR BIT(3) 64 #define WDT_WWPS_PEND_WSPR BIT(4) 65 66 #define WDT_WCLR_PRE BIT(5) 67 #define WDT_WCLR_PTV_OFF 2 68 69 #ifndef __KERNEL_STRICT_NAMES 70 #ifndef __ASSEMBLY__ 71 struct gpmc_cs { 72 u32 config1; /* 0x00 */ 73 u32 config2; /* 0x04 */ 74 u32 config3; /* 0x08 */ 75 u32 config4; /* 0x0C */ 76 u32 config5; /* 0x10 */ 77 u32 config6; /* 0x14 */ 78 u32 config7; /* 0x18 */ 79 u32 nand_cmd; /* 0x1C */ 80 u32 nand_adr; /* 0x20 */ 81 u32 nand_dat; /* 0x24 */ 82 u8 res[8]; /* blow up to 0x30 byte */ 83 }; 84 85 struct bch_res_0_3 { 86 u32 bch_result_x[4]; 87 }; 88 89 struct gpmc { 90 u8 res1[0x10]; 91 u32 sysconfig; /* 0x10 */ 92 u8 res2[0x4]; 93 u32 irqstatus; /* 0x18 */ 94 u32 irqenable; /* 0x1C */ 95 u8 res3[0x20]; 96 u32 timeout_control; /* 0x40 */ 97 u8 res4[0xC]; 98 u32 config; /* 0x50 */ 99 u32 status; /* 0x54 */ 100 u8 res5[0x8]; /* 0x58 */ 101 struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ 102 u8 res6[0x14]; /* 0x1E0 */ 103 u32 ecc_config; /* 0x1F4 */ 104 u32 ecc_control; /* 0x1F8 */ 105 u32 ecc_size_config; /* 0x1FC */ 106 u32 ecc1_result; /* 0x200 */ 107 u32 ecc2_result; /* 0x204 */ 108 u32 ecc3_result; /* 0x208 */ 109 u32 ecc4_result; /* 0x20C */ 110 u32 ecc5_result; /* 0x210 */ 111 u32 ecc6_result; /* 0x214 */ 112 u32 ecc7_result; /* 0x218 */ 113 u32 ecc8_result; /* 0x21C */ 114 u32 ecc9_result; /* 0x220 */ 115 u8 res7[12]; /* 0x224 */ 116 u32 testmomde_ctrl; /* 0x230 */ 117 u8 res8[12]; /* 0x234 */ 118 struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */ 119 }; 120 121 /* Used for board specific gpmc initialization */ 122 extern struct gpmc *gpmc_cfg; 123 124 #ifndef CONFIG_AM43XX 125 /* Encapsulating core pll registers */ 126 struct cm_wkuppll { 127 unsigned int wkclkstctrl; /* offset 0x00 */ 128 unsigned int wkctrlclkctrl; /* offset 0x04 */ 129 unsigned int wkgpio0clkctrl; /* offset 0x08 */ 130 unsigned int wkl4wkclkctrl; /* offset 0x0c */ 131 unsigned int resv2[4]; 132 unsigned int idlestdpllmpu; /* offset 0x20 */ 133 unsigned int resv3[2]; 134 unsigned int clkseldpllmpu; /* offset 0x2c */ 135 unsigned int resv4[1]; 136 unsigned int idlestdpllddr; /* offset 0x34 */ 137 unsigned int resv5[2]; 138 unsigned int clkseldpllddr; /* offset 0x40 */ 139 unsigned int resv6[4]; 140 unsigned int clkseldplldisp; /* offset 0x54 */ 141 unsigned int resv7[1]; 142 unsigned int idlestdpllcore; /* offset 0x5c */ 143 unsigned int resv8[2]; 144 unsigned int clkseldpllcore; /* offset 0x68 */ 145 unsigned int resv9[1]; 146 unsigned int idlestdpllper; /* offset 0x70 */ 147 unsigned int resv10[2]; 148 unsigned int clkdcoldodpllper; /* offset 0x7c */ 149 unsigned int divm4dpllcore; /* offset 0x80 */ 150 unsigned int divm5dpllcore; /* offset 0x84 */ 151 unsigned int clkmoddpllmpu; /* offset 0x88 */ 152 unsigned int clkmoddpllper; /* offset 0x8c */ 153 unsigned int clkmoddpllcore; /* offset 0x90 */ 154 unsigned int clkmoddpllddr; /* offset 0x94 */ 155 unsigned int clkmoddplldisp; /* offset 0x98 */ 156 unsigned int clkseldpllper; /* offset 0x9c */ 157 unsigned int divm2dpllddr; /* offset 0xA0 */ 158 unsigned int divm2dplldisp; /* offset 0xA4 */ 159 unsigned int divm2dpllmpu; /* offset 0xA8 */ 160 unsigned int divm2dpllper; /* offset 0xAC */ 161 unsigned int resv11[1]; 162 unsigned int wkup_uart0ctrl; /* offset 0xB4 */ 163 unsigned int wkup_i2c0ctrl; /* offset 0xB8 */ 164 unsigned int resv12[7]; 165 unsigned int divm6dpllcore; /* offset 0xD8 */ 166 }; 167 168 /** 169 * Encapsulating peripheral functional clocks 170 * pll registers 171 */ 172 struct cm_perpll { 173 unsigned int l4lsclkstctrl; /* offset 0x00 */ 174 unsigned int l3sclkstctrl; /* offset 0x04 */ 175 unsigned int l4fwclkstctrl; /* offset 0x08 */ 176 unsigned int l3clkstctrl; /* offset 0x0c */ 177 unsigned int resv1; 178 unsigned int cpgmac0clkctrl; /* offset 0x14 */ 179 unsigned int lcdclkctrl; /* offset 0x18 */ 180 unsigned int usb0clkctrl; /* offset 0x1C */ 181 unsigned int resv2; 182 unsigned int tptc0clkctrl; /* offset 0x24 */ 183 unsigned int emifclkctrl; /* offset 0x28 */ 184 unsigned int ocmcramclkctrl; /* offset 0x2c */ 185 unsigned int gpmcclkctrl; /* offset 0x30 */ 186 unsigned int mcasp0clkctrl; /* offset 0x34 */ 187 unsigned int uart5clkctrl; /* offset 0x38 */ 188 unsigned int mmc0clkctrl; /* offset 0x3C */ 189 unsigned int elmclkctrl; /* offset 0x40 */ 190 unsigned int i2c2clkctrl; /* offset 0x44 */ 191 unsigned int i2c1clkctrl; /* offset 0x48 */ 192 unsigned int spi0clkctrl; /* offset 0x4C */ 193 unsigned int spi1clkctrl; /* offset 0x50 */ 194 unsigned int resv3[3]; 195 unsigned int l4lsclkctrl; /* offset 0x60 */ 196 unsigned int l4fwclkctrl; /* offset 0x64 */ 197 unsigned int mcasp1clkctrl; /* offset 0x68 */ 198 unsigned int uart1clkctrl; /* offset 0x6C */ 199 unsigned int uart2clkctrl; /* offset 0x70 */ 200 unsigned int uart3clkctrl; /* offset 0x74 */ 201 unsigned int uart4clkctrl; /* offset 0x78 */ 202 unsigned int timer7clkctrl; /* offset 0x7C */ 203 unsigned int timer2clkctrl; /* offset 0x80 */ 204 unsigned int timer3clkctrl; /* offset 0x84 */ 205 unsigned int timer4clkctrl; /* offset 0x88 */ 206 unsigned int resv4[8]; 207 unsigned int gpio1clkctrl; /* offset 0xAC */ 208 unsigned int gpio2clkctrl; /* offset 0xB0 */ 209 unsigned int gpio3clkctrl; /* offset 0xB4 */ 210 unsigned int resv5; 211 unsigned int tpccclkctrl; /* offset 0xBC */ 212 unsigned int dcan0clkctrl; /* offset 0xC0 */ 213 unsigned int dcan1clkctrl; /* offset 0xC4 */ 214 unsigned int resv6[2]; 215 unsigned int emiffwclkctrl; /* offset 0xD0 */ 216 unsigned int epwmss0clkctrl; /* offset 0xD4 */ 217 unsigned int epwmss2clkctrl; /* offset 0xD8 */ 218 unsigned int l3instrclkctrl; /* offset 0xDC */ 219 unsigned int l3clkctrl; /* Offset 0xE0 */ 220 unsigned int resv8[4]; 221 unsigned int mmc1clkctrl; /* offset 0xF4 */ 222 unsigned int mmc2clkctrl; /* offset 0xF8 */ 223 unsigned int resv9[8]; 224 unsigned int l4hsclkstctrl; /* offset 0x11C */ 225 unsigned int l4hsclkctrl; /* offset 0x120 */ 226 unsigned int resv10[8]; 227 unsigned int cpswclkstctrl; /* offset 0x144 */ 228 unsigned int lcdcclkstctrl; /* offset 0x148 */ 229 }; 230 #else 231 /* Encapsulating core pll registers */ 232 struct cm_wkuppll { 233 unsigned int resv0[136]; 234 unsigned int wkl4wkclkctrl; /* offset 0x220 */ 235 unsigned int resv1[55]; 236 unsigned int wkclkstctrl; /* offset 0x300 */ 237 unsigned int resv2[15]; 238 unsigned int wkup_i2c0ctrl; /* offset 0x340 */ 239 unsigned int resv3; 240 unsigned int wkup_uart0ctrl; /* offset 0x348 */ 241 unsigned int resv4[5]; 242 unsigned int wkctrlclkctrl; /* offset 0x360 */ 243 unsigned int resv5; 244 unsigned int wkgpio0clkctrl; /* offset 0x368 */ 245 246 unsigned int resv6[109]; 247 unsigned int clkmoddpllcore; /* offset 0x520 */ 248 unsigned int idlestdpllcore; /* offset 0x524 */ 249 unsigned int resv61; 250 unsigned int clkseldpllcore; /* offset 0x52C */ 251 unsigned int resv7[2]; 252 unsigned int divm4dpllcore; /* offset 0x538 */ 253 unsigned int divm5dpllcore; /* offset 0x53C */ 254 unsigned int divm6dpllcore; /* offset 0x540 */ 255 256 unsigned int resv8[7]; 257 unsigned int clkmoddpllmpu; /* offset 0x560 */ 258 unsigned int idlestdpllmpu; /* offset 0x564 */ 259 unsigned int resv9; 260 unsigned int clkseldpllmpu; /* offset 0x56c */ 261 unsigned int divm2dpllmpu; /* offset 0x570 */ 262 263 unsigned int resv10[11]; 264 unsigned int clkmoddpllddr; /* offset 0x5A0 */ 265 unsigned int idlestdpllddr; /* offset 0x5A4 */ 266 unsigned int resv11; 267 unsigned int clkseldpllddr; /* offset 0x5AC */ 268 unsigned int divm2dpllddr; /* offset 0x5B0 */ 269 270 unsigned int resv12[11]; 271 unsigned int clkmoddpllper; /* offset 0x5E0 */ 272 unsigned int idlestdpllper; /* offset 0x5E4 */ 273 unsigned int resv13; 274 unsigned int clkseldpllper; /* offset 0x5EC */ 275 unsigned int divm2dpllper; /* offset 0x5F0 */ 276 unsigned int resv14[8]; 277 unsigned int clkdcoldodpllper; /* offset 0x614 */ 278 279 unsigned int resv15[2]; 280 unsigned int clkmoddplldisp; /* offset 0x620 */ 281 unsigned int resv16[2]; 282 unsigned int clkseldplldisp; /* offset 0x62C */ 283 unsigned int divm2dplldisp; /* offset 0x630 */ 284 }; 285 286 /* 287 * Encapsulating peripheral functional clocks 288 * pll registers 289 */ 290 struct cm_perpll { 291 unsigned int l3clkstctrl; /* offset 0x00 */ 292 unsigned int resv0[7]; 293 unsigned int l3clkctrl; /* Offset 0x20 */ 294 unsigned int resv1[7]; 295 unsigned int l3instrclkctrl; /* offset 0x40 */ 296 unsigned int resv2[3]; 297 unsigned int ocmcramclkctrl; /* offset 0x50 */ 298 unsigned int resv3[9]; 299 unsigned int tpccclkctrl; /* offset 0x78 */ 300 unsigned int resv4; 301 unsigned int tptc0clkctrl; /* offset 0x80 */ 302 303 unsigned int resv5[7]; 304 unsigned int l4hsclkctrl; /* offset 0x0A0 */ 305 unsigned int resv6; 306 unsigned int l4fwclkctrl; /* offset 0x0A8 */ 307 unsigned int resv7[85]; 308 unsigned int l3sclkstctrl; /* offset 0x200 */ 309 unsigned int resv8[7]; 310 unsigned int gpmcclkctrl; /* offset 0x220 */ 311 unsigned int resv9[5]; 312 unsigned int mcasp0clkctrl; /* offset 0x238 */ 313 unsigned int resv10; 314 unsigned int mcasp1clkctrl; /* offset 0x240 */ 315 unsigned int resv11; 316 unsigned int mmc2clkctrl; /* offset 0x248 */ 317 unsigned int resv12[5]; 318 unsigned int usb0clkctrl; /* offset 0x260 */ 319 unsigned int resv13[103]; 320 unsigned int l4lsclkstctrl; /* offset 0x400 */ 321 unsigned int resv14[7]; 322 unsigned int l4lsclkctrl; /* offset 0x420 */ 323 unsigned int resv15; 324 unsigned int dcan0clkctrl; /* offset 0x428 */ 325 unsigned int resv16; 326 unsigned int dcan1clkctrl; /* offset 0x430 */ 327 unsigned int resv17[13]; 328 unsigned int elmclkctrl; /* offset 0x468 */ 329 330 unsigned int resv18[3]; 331 unsigned int gpio1clkctrl; /* offset 0x478 */ 332 unsigned int resv19; 333 unsigned int gpio2clkctrl; /* offset 0x480 */ 334 unsigned int resv20; 335 unsigned int gpio3clkctrl; /* offset 0x488 */ 336 unsigned int resv21[7]; 337 338 unsigned int i2c1clkctrl; /* offset 0x4A8 */ 339 unsigned int resv22; 340 unsigned int i2c2clkctrl; /* offset 0x4B0 */ 341 unsigned int resv23[3]; 342 unsigned int mmc0clkctrl; /* offset 0x4C0 */ 343 unsigned int resv24; 344 unsigned int mmc1clkctrl; /* offset 0x4C8 */ 345 346 unsigned int resv25[13]; 347 unsigned int spi0clkctrl; /* offset 0x500 */ 348 unsigned int resv26; 349 unsigned int spi1clkctrl; /* offset 0x508 */ 350 unsigned int resv27[9]; 351 unsigned int timer2clkctrl; /* offset 0x530 */ 352 unsigned int resv28; 353 unsigned int timer3clkctrl; /* offset 0x538 */ 354 unsigned int resv29; 355 unsigned int timer4clkctrl; /* offset 0x540 */ 356 unsigned int resv30[5]; 357 unsigned int timer7clkctrl; /* offset 0x558 */ 358 359 unsigned int resv31[9]; 360 unsigned int uart1clkctrl; /* offset 0x580 */ 361 unsigned int resv32; 362 unsigned int uart2clkctrl; /* offset 0x588 */ 363 unsigned int resv33; 364 unsigned int uart3clkctrl; /* offset 0x590 */ 365 unsigned int resv34; 366 unsigned int uart4clkctrl; /* offset 0x598 */ 367 unsigned int resv35; 368 unsigned int uart5clkctrl; /* offset 0x5A0 */ 369 unsigned int resv36[87]; 370 371 unsigned int emifclkstctrl; /* offset 0x700 */ 372 unsigned int resv361[7]; 373 unsigned int emifclkctrl; /* offset 0x720 */ 374 unsigned int resv37[3]; 375 unsigned int emiffwclkctrl; /* offset 0x730 */ 376 unsigned int resv371; 377 unsigned int otfaemifclkctrl; /* offset 0x738 */ 378 unsigned int resv38[57]; 379 unsigned int lcdclkctrl; /* offset 0x820 */ 380 unsigned int resv39[183]; 381 unsigned int cpswclkstctrl; /* offset 0xB00 */ 382 unsigned int resv40[7]; 383 unsigned int cpgmac0clkctrl; /* offset 0xB20 */ 384 }; 385 #endif /* CONFIG_AM43XX */ 386 387 /* Encapsulating Display pll registers */ 388 struct cm_dpll { 389 unsigned int resv1[2]; 390 unsigned int clktimer2clk; /* offset 0x08 */ 391 unsigned int resv2[10]; 392 unsigned int clklcdcpixelclk; /* offset 0x34 */ 393 }; 394 395 /* Control Module RTC registers */ 396 struct cm_rtc { 397 unsigned int rtcclkctrl; /* offset 0x0 */ 398 unsigned int clkstctrl; /* offset 0x4 */ 399 }; 400 401 /* Watchdog timer registers */ 402 struct wd_timer { 403 unsigned int resv1[4]; 404 unsigned int wdtwdsc; /* offset 0x010 */ 405 unsigned int wdtwdst; /* offset 0x014 */ 406 unsigned int wdtwisr; /* offset 0x018 */ 407 unsigned int wdtwier; /* offset 0x01C */ 408 unsigned int wdtwwer; /* offset 0x020 */ 409 unsigned int wdtwclr; /* offset 0x024 */ 410 unsigned int wdtwcrr; /* offset 0x028 */ 411 unsigned int wdtwldr; /* offset 0x02C */ 412 unsigned int wdtwtgr; /* offset 0x030 */ 413 unsigned int wdtwwps; /* offset 0x034 */ 414 unsigned int resv2[3]; 415 unsigned int wdtwdly; /* offset 0x044 */ 416 unsigned int wdtwspr; /* offset 0x048 */ 417 unsigned int resv3[1]; 418 unsigned int wdtwqeoi; /* offset 0x050 */ 419 unsigned int wdtwqstar; /* offset 0x054 */ 420 unsigned int wdtwqsta; /* offset 0x058 */ 421 unsigned int wdtwqens; /* offset 0x05C */ 422 unsigned int wdtwqenc; /* offset 0x060 */ 423 unsigned int resv4[39]; 424 unsigned int wdt_unfr; /* offset 0x100 */ 425 }; 426 427 /* Timer 32 bit registers */ 428 struct gptimer { 429 unsigned int tidr; /* offset 0x00 */ 430 unsigned char res1[12]; 431 unsigned int tiocp_cfg; /* offset 0x10 */ 432 unsigned char res2[12]; 433 unsigned int tier; /* offset 0x20 */ 434 unsigned int tistatr; /* offset 0x24 */ 435 unsigned int tistat; /* offset 0x28 */ 436 unsigned int tisr; /* offset 0x2c */ 437 unsigned int tcicr; /* offset 0x30 */ 438 unsigned int twer; /* offset 0x34 */ 439 unsigned int tclr; /* offset 0x38 */ 440 unsigned int tcrr; /* offset 0x3c */ 441 unsigned int tldr; /* offset 0x40 */ 442 unsigned int ttgr; /* offset 0x44 */ 443 unsigned int twpc; /* offset 0x48 */ 444 unsigned int tmar; /* offset 0x4c */ 445 unsigned int tcar1; /* offset 0x50 */ 446 unsigned int tscir; /* offset 0x54 */ 447 unsigned int tcar2; /* offset 0x58 */ 448 }; 449 450 /* RTC Registers */ 451 struct rtc_regs { 452 unsigned int res[21]; 453 unsigned int osc; /* offset 0x54 */ 454 unsigned int res2[5]; 455 unsigned int kick0r; /* offset 0x6c */ 456 unsigned int kick1r; /* offset 0x70 */ 457 }; 458 459 /* UART Registers */ 460 struct uart_sys { 461 unsigned int resv1[21]; 462 unsigned int uartsyscfg; /* offset 0x54 */ 463 unsigned int uartsyssts; /* offset 0x58 */ 464 }; 465 466 /* VTP Registers */ 467 struct vtp_reg { 468 unsigned int vtp0ctrlreg; 469 }; 470 471 /* Control Status Register */ 472 struct ctrl_stat { 473 unsigned int resv1[16]; 474 unsigned int statusreg; /* ofset 0x40 */ 475 unsigned int resv2[51]; 476 unsigned int secure_emif_sdram_config; /* offset 0x0110 */ 477 }; 478 479 /* AM33XX GPIO registers */ 480 #define OMAP_GPIO_REVISION 0x0000 481 #define OMAP_GPIO_SYSCONFIG 0x0010 482 #define OMAP_GPIO_SYSSTATUS 0x0114 483 #define OMAP_GPIO_IRQSTATUS1 0x002c 484 #define OMAP_GPIO_IRQSTATUS2 0x0030 485 #define OMAP_GPIO_CTRL 0x0130 486 #define OMAP_GPIO_OE 0x0134 487 #define OMAP_GPIO_DATAIN 0x0138 488 #define OMAP_GPIO_DATAOUT 0x013c 489 #define OMAP_GPIO_LEVELDETECT0 0x0140 490 #define OMAP_GPIO_LEVELDETECT1 0x0144 491 #define OMAP_GPIO_RISINGDETECT 0x0148 492 #define OMAP_GPIO_FALLINGDETECT 0x014c 493 #define OMAP_GPIO_DEBOUNCE_EN 0x0150 494 #define OMAP_GPIO_DEBOUNCE_VAL 0x0154 495 #define OMAP_GPIO_CLEARDATAOUT 0x0190 496 #define OMAP_GPIO_SETDATAOUT 0x0194 497 498 /* Control Device Register */ 499 struct ctrl_dev { 500 unsigned int deviceid; /* offset 0x00 */ 501 unsigned int resv1[7]; 502 unsigned int usb_ctrl0; /* offset 0x20 */ 503 unsigned int resv2; 504 unsigned int usb_ctrl1; /* offset 0x28 */ 505 unsigned int resv3; 506 unsigned int macid0l; /* offset 0x30 */ 507 unsigned int macid0h; /* offset 0x34 */ 508 unsigned int macid1l; /* offset 0x38 */ 509 unsigned int macid1h; /* offset 0x3c */ 510 unsigned int resv4[4]; 511 unsigned int miisel; /* offset 0x50 */ 512 }; 513 514 /* gmii_sel register defines */ 515 #define GMII1_SEL_MII 0x0 516 #define GMII1_SEL_RMII 0x1 517 #define GMII1_SEL_RGMII 0x2 518 #define GMII2_SEL_MII 0x0 519 #define GMII2_SEL_RMII 0x4 520 #define GMII2_SEL_RGMII 0x8 521 #define RGMII1_IDMODE BIT(4) 522 #define RGMII2_IDMODE BIT(5) 523 #define RMII1_IO_CLK_EN BIT(6) 524 #define RMII2_IO_CLK_EN BIT(7) 525 526 #define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII) 527 #define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII) 528 #define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII) 529 #define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE) 530 #define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN) 531 532 /* PWMSS */ 533 struct pwmss_regs { 534 unsigned int idver; 535 unsigned int sysconfig; 536 unsigned int clkconfig; 537 unsigned int clkstatus; 538 }; 539 #define ECAP_CLK_EN BIT(0) 540 #define ECAP_CLK_STOP_REQ BIT(1) 541 542 struct pwmss_ecap_regs { 543 unsigned int tsctr; 544 unsigned int ctrphs; 545 unsigned int cap1; 546 unsigned int cap2; 547 unsigned int cap3; 548 unsigned int cap4; 549 unsigned int resv1[4]; 550 unsigned short ecctl1; 551 unsigned short ecctl2; 552 }; 553 554 /* Capture Control register 2 */ 555 #define ECTRL2_SYNCOSEL_MASK (0x03 << 6) 556 #define ECTRL2_MDSL_ECAP BIT(9) 557 #define ECTRL2_CTRSTP_FREERUN BIT(4) 558 #define ECTRL2_PLSL_LOW BIT(10) 559 #define ECTRL2_SYNC_EN BIT(5) 560 561 #endif /* __ASSEMBLY__ */ 562 #endif /* __KERNEL_STRICT_NAMES */ 563 564 #endif /* _AM33XX_CPU_H */ 565