1 /* 2 * cpu.h 3 * 4 * AM33xx specific header file 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef _AM33XX_CPU_H 20 #define _AM33XX_CPU_H 21 22 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 23 #include <asm/types.h> 24 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 25 26 #include <asm/arch/hardware.h> 27 28 #define BIT(x) (1 << x) 29 #define CL_BIT(x) (0 << x) 30 31 /* Timer register bits */ 32 #define TCLR_ST BIT(0) /* Start=1 Stop=0 */ 33 #define TCLR_AR BIT(1) /* Auto reload */ 34 #define TCLR_PRE BIT(5) /* Pre-scaler enable */ 35 #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */ 36 #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */ 37 38 /* device type */ 39 #define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) 40 #define TST_DEVICE 0x0 41 #define EMU_DEVICE 0x1 42 #define HS_DEVICE 0x2 43 #define GP_DEVICE 0x3 44 45 /* cpu-id for AM33XX family */ 46 #define AM335X 0xB944 47 #define DEVICE_ID 0x44E10600 48 49 /* This gives the status of the boot mode pins on the evm */ 50 #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ 51 | BIT(3) | BIT(4)) 52 53 /* Reset control */ 54 #ifdef CONFIG_AM33XX 55 #define PRM_RSTCTRL 0x44E00F00 56 #define PRM_RSTST 0x44E00F08 57 #endif 58 #define PRM_RSTCTRL_RESET 0x01 59 #define PRM_RSTST_WARM_RESET_MASK 0x232 60 61 #ifndef __KERNEL_STRICT_NAMES 62 #ifndef __ASSEMBLY__ 63 /* Encapsulating core pll registers */ 64 struct cm_wkuppll { 65 unsigned int wkclkstctrl; /* offset 0x00 */ 66 unsigned int wkctrlclkctrl; /* offset 0x04 */ 67 unsigned int wkgpio0clkctrl; /* offset 0x08 */ 68 unsigned int wkl4wkclkctrl; /* offset 0x0c */ 69 unsigned int resv2[4]; 70 unsigned int idlestdpllmpu; /* offset 0x20 */ 71 unsigned int resv3[2]; 72 unsigned int clkseldpllmpu; /* offset 0x2c */ 73 unsigned int resv4[1]; 74 unsigned int idlestdpllddr; /* offset 0x34 */ 75 unsigned int resv5[2]; 76 unsigned int clkseldpllddr; /* offset 0x40 */ 77 unsigned int resv6[4]; 78 unsigned int clkseldplldisp; /* offset 0x54 */ 79 unsigned int resv7[1]; 80 unsigned int idlestdpllcore; /* offset 0x5c */ 81 unsigned int resv8[2]; 82 unsigned int clkseldpllcore; /* offset 0x68 */ 83 unsigned int resv9[1]; 84 unsigned int idlestdpllper; /* offset 0x70 */ 85 unsigned int resv10[3]; 86 unsigned int divm4dpllcore; /* offset 0x80 */ 87 unsigned int divm5dpllcore; /* offset 0x84 */ 88 unsigned int clkmoddpllmpu; /* offset 0x88 */ 89 unsigned int clkmoddpllper; /* offset 0x8c */ 90 unsigned int clkmoddpllcore; /* offset 0x90 */ 91 unsigned int clkmoddpllddr; /* offset 0x94 */ 92 unsigned int clkmoddplldisp; /* offset 0x98 */ 93 unsigned int clkseldpllper; /* offset 0x9c */ 94 unsigned int divm2dpllddr; /* offset 0xA0 */ 95 unsigned int divm2dplldisp; /* offset 0xA4 */ 96 unsigned int divm2dpllmpu; /* offset 0xA8 */ 97 unsigned int divm2dpllper; /* offset 0xAC */ 98 unsigned int resv11[1]; 99 unsigned int wkup_uart0ctrl; /* offset 0xB4 */ 100 unsigned int wkup_i2c0ctrl; /* offset 0xB8 */ 101 unsigned int resv12[7]; 102 unsigned int divm6dpllcore; /* offset 0xD8 */ 103 }; 104 105 /** 106 * Encapsulating peripheral functional clocks 107 * pll registers 108 */ 109 struct cm_perpll { 110 unsigned int l4lsclkstctrl; /* offset 0x00 */ 111 unsigned int l3sclkstctrl; /* offset 0x04 */ 112 unsigned int l4fwclkstctrl; /* offset 0x08 */ 113 unsigned int l3clkstctrl; /* offset 0x0c */ 114 unsigned int resv1; 115 unsigned int cpgmac0clkctrl; /* offset 0x14 */ 116 unsigned int lcdclkctrl; /* offset 0x18 */ 117 unsigned int usb0clkctrl; /* offset 0x1C */ 118 unsigned int resv2; 119 unsigned int tptc0clkctrl; /* offset 0x24 */ 120 unsigned int emifclkctrl; /* offset 0x28 */ 121 unsigned int ocmcramclkctrl; /* offset 0x2c */ 122 unsigned int gpmcclkctrl; /* offset 0x30 */ 123 unsigned int mcasp0clkctrl; /* offset 0x34 */ 124 unsigned int uart5clkctrl; /* offset 0x38 */ 125 unsigned int mmc0clkctrl; /* offset 0x3C */ 126 unsigned int elmclkctrl; /* offset 0x40 */ 127 unsigned int i2c2clkctrl; /* offset 0x44 */ 128 unsigned int i2c1clkctrl; /* offset 0x48 */ 129 unsigned int spi0clkctrl; /* offset 0x4C */ 130 unsigned int spi1clkctrl; /* offset 0x50 */ 131 unsigned int resv3[3]; 132 unsigned int l4lsclkctrl; /* offset 0x60 */ 133 unsigned int l4fwclkctrl; /* offset 0x64 */ 134 unsigned int mcasp1clkctrl; /* offset 0x68 */ 135 unsigned int uart1clkctrl; /* offset 0x6C */ 136 unsigned int uart2clkctrl; /* offset 0x70 */ 137 unsigned int uart3clkctrl; /* offset 0x74 */ 138 unsigned int uart4clkctrl; /* offset 0x78 */ 139 unsigned int timer7clkctrl; /* offset 0x7C */ 140 unsigned int timer2clkctrl; /* offset 0x80 */ 141 unsigned int timer3clkctrl; /* offset 0x84 */ 142 unsigned int timer4clkctrl; /* offset 0x88 */ 143 unsigned int resv4[8]; 144 unsigned int gpio1clkctrl; /* offset 0xAC */ 145 unsigned int gpio2clkctrl; /* offset 0xB0 */ 146 unsigned int gpio3clkctrl; /* offset 0xB4 */ 147 unsigned int resv5; 148 unsigned int tpccclkctrl; /* offset 0xBC */ 149 unsigned int dcan0clkctrl; /* offset 0xC0 */ 150 unsigned int dcan1clkctrl; /* offset 0xC4 */ 151 unsigned int resv6[2]; 152 unsigned int emiffwclkctrl; /* offset 0xD0 */ 153 unsigned int resv7[2]; 154 unsigned int l3instrclkctrl; /* offset 0xDC */ 155 unsigned int l3clkctrl; /* Offset 0xE0 */ 156 unsigned int resv8[4]; 157 unsigned int mmc1clkctrl; /* offset 0xF4 */ 158 unsigned int mmc2clkctrl; /* offset 0xF8 */ 159 unsigned int resv9[8]; 160 unsigned int l4hsclkstctrl; /* offset 0x11C */ 161 unsigned int l4hsclkctrl; /* offset 0x120 */ 162 unsigned int resv10[8]; 163 unsigned int cpswclkstctrl; /* offset 0x144 */ 164 }; 165 166 /* Encapsulating Display pll registers */ 167 struct cm_dpll { 168 unsigned int resv1[2]; 169 unsigned int clktimer2clk; /* offset 0x08 */ 170 }; 171 172 /* Control Module RTC registers */ 173 struct cm_rtc { 174 unsigned int rtcclkctrl; /* offset 0x0 */ 175 unsigned int clkstctrl; /* offset 0x4 */ 176 }; 177 178 /* Watchdog timer registers */ 179 struct wd_timer { 180 unsigned int resv1[4]; 181 unsigned int wdtwdsc; /* offset 0x010 */ 182 unsigned int wdtwdst; /* offset 0x014 */ 183 unsigned int wdtwisr; /* offset 0x018 */ 184 unsigned int wdtwier; /* offset 0x01C */ 185 unsigned int wdtwwer; /* offset 0x020 */ 186 unsigned int wdtwclr; /* offset 0x024 */ 187 unsigned int wdtwcrr; /* offset 0x028 */ 188 unsigned int wdtwldr; /* offset 0x02C */ 189 unsigned int wdtwtgr; /* offset 0x030 */ 190 unsigned int wdtwwps; /* offset 0x034 */ 191 unsigned int resv2[3]; 192 unsigned int wdtwdly; /* offset 0x044 */ 193 unsigned int wdtwspr; /* offset 0x048 */ 194 unsigned int resv3[1]; 195 unsigned int wdtwqeoi; /* offset 0x050 */ 196 unsigned int wdtwqstar; /* offset 0x054 */ 197 unsigned int wdtwqsta; /* offset 0x058 */ 198 unsigned int wdtwqens; /* offset 0x05C */ 199 unsigned int wdtwqenc; /* offset 0x060 */ 200 unsigned int resv4[39]; 201 unsigned int wdt_unfr; /* offset 0x100 */ 202 }; 203 204 /* Timer 32 bit registers */ 205 struct gptimer { 206 unsigned int tidr; /* offset 0x00 */ 207 unsigned char res1[12]; 208 unsigned int tiocp_cfg; /* offset 0x10 */ 209 unsigned char res2[12]; 210 unsigned int tier; /* offset 0x20 */ 211 unsigned int tistatr; /* offset 0x24 */ 212 unsigned int tistat; /* offset 0x28 */ 213 unsigned int tisr; /* offset 0x2c */ 214 unsigned int tcicr; /* offset 0x30 */ 215 unsigned int twer; /* offset 0x34 */ 216 unsigned int tclr; /* offset 0x38 */ 217 unsigned int tcrr; /* offset 0x3c */ 218 unsigned int tldr; /* offset 0x40 */ 219 unsigned int ttgr; /* offset 0x44 */ 220 unsigned int twpc; /* offset 0x48 */ 221 unsigned int tmar; /* offset 0x4c */ 222 unsigned int tcar1; /* offset 0x50 */ 223 unsigned int tscir; /* offset 0x54 */ 224 unsigned int tcar2; /* offset 0x58 */ 225 }; 226 227 /* RTC Registers */ 228 struct rtc_regs { 229 unsigned int res[21]; 230 unsigned int osc; /* offset 0x54 */ 231 unsigned int res2[5]; 232 unsigned int kick0r; /* offset 0x6c */ 233 unsigned int kick1r; /* offset 0x70 */ 234 }; 235 236 /* UART Registers */ 237 struct uart_sys { 238 unsigned int resv1[21]; 239 unsigned int uartsyscfg; /* offset 0x54 */ 240 unsigned int uartsyssts; /* offset 0x58 */ 241 }; 242 243 /* VTP Registers */ 244 struct vtp_reg { 245 unsigned int vtp0ctrlreg; 246 }; 247 248 /* Control Status Register */ 249 struct ctrl_stat { 250 unsigned int resv1[16]; 251 unsigned int statusreg; /* ofset 0x40 */ 252 unsigned int resv2[51]; 253 unsigned int secure_emif_sdram_config; /* offset 0x0110 */ 254 }; 255 256 /* AM33XX GPIO registers */ 257 #define OMAP_GPIO_REVISION 0x0000 258 #define OMAP_GPIO_SYSCONFIG 0x0010 259 #define OMAP_GPIO_SYSSTATUS 0x0114 260 #define OMAP_GPIO_IRQSTATUS1 0x002c 261 #define OMAP_GPIO_IRQSTATUS2 0x0030 262 #define OMAP_GPIO_CTRL 0x0130 263 #define OMAP_GPIO_OE 0x0134 264 #define OMAP_GPIO_DATAIN 0x0138 265 #define OMAP_GPIO_DATAOUT 0x013c 266 #define OMAP_GPIO_LEVELDETECT0 0x0140 267 #define OMAP_GPIO_LEVELDETECT1 0x0144 268 #define OMAP_GPIO_RISINGDETECT 0x0148 269 #define OMAP_GPIO_FALLINGDETECT 0x014c 270 #define OMAP_GPIO_DEBOUNCE_EN 0x0150 271 #define OMAP_GPIO_DEBOUNCE_VAL 0x0154 272 #define OMAP_GPIO_CLEARDATAOUT 0x0190 273 #define OMAP_GPIO_SETDATAOUT 0x0194 274 275 /* Control Device Register */ 276 struct ctrl_dev { 277 unsigned int deviceid; /* offset 0x00 */ 278 unsigned int resv1[11]; 279 unsigned int macid0l; /* offset 0x30 */ 280 unsigned int macid0h; /* offset 0x34 */ 281 unsigned int macid1l; /* offset 0x38 */ 282 unsigned int macid1h; /* offset 0x3c */ 283 unsigned int resv2[4]; 284 unsigned int miisel; /* offset 0x50 */ 285 }; 286 #endif /* __ASSEMBLY__ */ 287 #endif /* __KERNEL_STRICT_NAMES */ 288 289 #endif /* _AM33XX_CPU_H */ 290