1 /* 2 * cpu.h 3 * 4 * AM33xx specific header file 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef _AM33XX_CPU_H 20 #define _AM33XX_CPU_H 21 22 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 23 #include <asm/types.h> 24 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 25 26 #include <asm/arch/hardware.h> 27 28 #define BIT(x) (1 << x) 29 #define CL_BIT(x) (0 << x) 30 31 /* Timer register bits */ 32 #define TCLR_ST BIT(0) /* Start=1 Stop=0 */ 33 #define TCLR_AR BIT(1) /* Auto reload */ 34 #define TCLR_PRE BIT(5) /* Pre-scaler enable */ 35 #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */ 36 #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */ 37 38 /* device type */ 39 #define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) 40 #define TST_DEVICE 0x0 41 #define EMU_DEVICE 0x1 42 #define HS_DEVICE 0x2 43 #define GP_DEVICE 0x3 44 45 /* cpu-id for AM33XX and TI81XX family */ 46 #define AM335X 0xB944 47 #define TI81XX 0xB81E 48 #define DEVICE_ID (CTRL_BASE + 0x0600) 49 50 /* This gives the status of the boot mode pins on the evm */ 51 #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ 52 | BIT(3) | BIT(4)) 53 54 /* Reset control */ 55 #ifdef CONFIG_AM33XX 56 #define PRM_RSTCTRL (PRCM_BASE + 0x0F00) 57 #elif defined(CONFIG_TI814X) 58 #define PRM_RSTCTRL (PRCM_BASE + 0x00A0) 59 #endif 60 #define PRM_RSTST (PRM_RSTCTRL + 8) 61 #define PRM_RSTCTRL_RESET 0x01 62 #define PRM_RSTST_WARM_RESET_MASK 0x232 63 64 #ifndef __KERNEL_STRICT_NAMES 65 #ifndef __ASSEMBLY__ 66 struct gpmc_cs { 67 u32 config1; /* 0x00 */ 68 u32 config2; /* 0x04 */ 69 u32 config3; /* 0x08 */ 70 u32 config4; /* 0x0C */ 71 u32 config5; /* 0x10 */ 72 u32 config6; /* 0x14 */ 73 u32 config7; /* 0x18 */ 74 u32 nand_cmd; /* 0x1C */ 75 u32 nand_adr; /* 0x20 */ 76 u32 nand_dat; /* 0x24 */ 77 u8 res[8]; /* blow up to 0x30 byte */ 78 }; 79 80 struct bch_res_0_3 { 81 u32 bch_result_x[4]; 82 }; 83 84 struct gpmc { 85 u8 res1[0x10]; 86 u32 sysconfig; /* 0x10 */ 87 u8 res2[0x4]; 88 u32 irqstatus; /* 0x18 */ 89 u32 irqenable; /* 0x1C */ 90 u8 res3[0x20]; 91 u32 timeout_control; /* 0x40 */ 92 u8 res4[0xC]; 93 u32 config; /* 0x50 */ 94 u32 status; /* 0x54 */ 95 u8 res5[0x8]; /* 0x58 */ 96 struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ 97 u8 res6[0x14]; /* 0x1E0 */ 98 u32 ecc_config; /* 0x1F4 */ 99 u32 ecc_control; /* 0x1F8 */ 100 u32 ecc_size_config; /* 0x1FC */ 101 u32 ecc1_result; /* 0x200 */ 102 u32 ecc2_result; /* 0x204 */ 103 u32 ecc3_result; /* 0x208 */ 104 u32 ecc4_result; /* 0x20C */ 105 u32 ecc5_result; /* 0x210 */ 106 u32 ecc6_result; /* 0x214 */ 107 u32 ecc7_result; /* 0x218 */ 108 u32 ecc8_result; /* 0x21C */ 109 u32 ecc9_result; /* 0x220 */ 110 u8 res7[12]; /* 0x224 */ 111 u32 testmomde_ctrl; /* 0x230 */ 112 u8 res8[12]; /* 0x234 */ 113 struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */ 114 }; 115 116 /* Used for board specific gpmc initialization */ 117 extern struct gpmc *gpmc_cfg; 118 119 /* Encapsulating core pll registers */ 120 struct cm_wkuppll { 121 unsigned int wkclkstctrl; /* offset 0x00 */ 122 unsigned int wkctrlclkctrl; /* offset 0x04 */ 123 unsigned int wkgpio0clkctrl; /* offset 0x08 */ 124 unsigned int wkl4wkclkctrl; /* offset 0x0c */ 125 unsigned int resv2[4]; 126 unsigned int idlestdpllmpu; /* offset 0x20 */ 127 unsigned int resv3[2]; 128 unsigned int clkseldpllmpu; /* offset 0x2c */ 129 unsigned int resv4[1]; 130 unsigned int idlestdpllddr; /* offset 0x34 */ 131 unsigned int resv5[2]; 132 unsigned int clkseldpllddr; /* offset 0x40 */ 133 unsigned int resv6[4]; 134 unsigned int clkseldplldisp; /* offset 0x54 */ 135 unsigned int resv7[1]; 136 unsigned int idlestdpllcore; /* offset 0x5c */ 137 unsigned int resv8[2]; 138 unsigned int clkseldpllcore; /* offset 0x68 */ 139 unsigned int resv9[1]; 140 unsigned int idlestdpllper; /* offset 0x70 */ 141 unsigned int resv10[2]; 142 unsigned int clkdcoldodpllper; /* offset 0x7c */ 143 unsigned int divm4dpllcore; /* offset 0x80 */ 144 unsigned int divm5dpllcore; /* offset 0x84 */ 145 unsigned int clkmoddpllmpu; /* offset 0x88 */ 146 unsigned int clkmoddpllper; /* offset 0x8c */ 147 unsigned int clkmoddpllcore; /* offset 0x90 */ 148 unsigned int clkmoddpllddr; /* offset 0x94 */ 149 unsigned int clkmoddplldisp; /* offset 0x98 */ 150 unsigned int clkseldpllper; /* offset 0x9c */ 151 unsigned int divm2dpllddr; /* offset 0xA0 */ 152 unsigned int divm2dplldisp; /* offset 0xA4 */ 153 unsigned int divm2dpllmpu; /* offset 0xA8 */ 154 unsigned int divm2dpllper; /* offset 0xAC */ 155 unsigned int resv11[1]; 156 unsigned int wkup_uart0ctrl; /* offset 0xB4 */ 157 unsigned int wkup_i2c0ctrl; /* offset 0xB8 */ 158 unsigned int resv12[7]; 159 unsigned int divm6dpllcore; /* offset 0xD8 */ 160 }; 161 162 /** 163 * Encapsulating peripheral functional clocks 164 * pll registers 165 */ 166 struct cm_perpll { 167 unsigned int l4lsclkstctrl; /* offset 0x00 */ 168 unsigned int l3sclkstctrl; /* offset 0x04 */ 169 unsigned int l4fwclkstctrl; /* offset 0x08 */ 170 unsigned int l3clkstctrl; /* offset 0x0c */ 171 unsigned int resv1; 172 unsigned int cpgmac0clkctrl; /* offset 0x14 */ 173 unsigned int lcdclkctrl; /* offset 0x18 */ 174 unsigned int usb0clkctrl; /* offset 0x1C */ 175 unsigned int resv2; 176 unsigned int tptc0clkctrl; /* offset 0x24 */ 177 unsigned int emifclkctrl; /* offset 0x28 */ 178 unsigned int ocmcramclkctrl; /* offset 0x2c */ 179 unsigned int gpmcclkctrl; /* offset 0x30 */ 180 unsigned int mcasp0clkctrl; /* offset 0x34 */ 181 unsigned int uart5clkctrl; /* offset 0x38 */ 182 unsigned int mmc0clkctrl; /* offset 0x3C */ 183 unsigned int elmclkctrl; /* offset 0x40 */ 184 unsigned int i2c2clkctrl; /* offset 0x44 */ 185 unsigned int i2c1clkctrl; /* offset 0x48 */ 186 unsigned int spi0clkctrl; /* offset 0x4C */ 187 unsigned int spi1clkctrl; /* offset 0x50 */ 188 unsigned int resv3[3]; 189 unsigned int l4lsclkctrl; /* offset 0x60 */ 190 unsigned int l4fwclkctrl; /* offset 0x64 */ 191 unsigned int mcasp1clkctrl; /* offset 0x68 */ 192 unsigned int uart1clkctrl; /* offset 0x6C */ 193 unsigned int uart2clkctrl; /* offset 0x70 */ 194 unsigned int uart3clkctrl; /* offset 0x74 */ 195 unsigned int uart4clkctrl; /* offset 0x78 */ 196 unsigned int timer7clkctrl; /* offset 0x7C */ 197 unsigned int timer2clkctrl; /* offset 0x80 */ 198 unsigned int timer3clkctrl; /* offset 0x84 */ 199 unsigned int timer4clkctrl; /* offset 0x88 */ 200 unsigned int resv4[8]; 201 unsigned int gpio1clkctrl; /* offset 0xAC */ 202 unsigned int gpio2clkctrl; /* offset 0xB0 */ 203 unsigned int gpio3clkctrl; /* offset 0xB4 */ 204 unsigned int resv5; 205 unsigned int tpccclkctrl; /* offset 0xBC */ 206 unsigned int dcan0clkctrl; /* offset 0xC0 */ 207 unsigned int dcan1clkctrl; /* offset 0xC4 */ 208 unsigned int resv6[2]; 209 unsigned int emiffwclkctrl; /* offset 0xD0 */ 210 unsigned int resv7[2]; 211 unsigned int l3instrclkctrl; /* offset 0xDC */ 212 unsigned int l3clkctrl; /* Offset 0xE0 */ 213 unsigned int resv8[4]; 214 unsigned int mmc1clkctrl; /* offset 0xF4 */ 215 unsigned int mmc2clkctrl; /* offset 0xF8 */ 216 unsigned int resv9[8]; 217 unsigned int l4hsclkstctrl; /* offset 0x11C */ 218 unsigned int l4hsclkctrl; /* offset 0x120 */ 219 unsigned int resv10[8]; 220 unsigned int cpswclkstctrl; /* offset 0x144 */ 221 }; 222 223 /* Encapsulating Display pll registers */ 224 struct cm_dpll { 225 unsigned int resv1[2]; 226 unsigned int clktimer2clk; /* offset 0x08 */ 227 }; 228 229 /* Control Module RTC registers */ 230 struct cm_rtc { 231 unsigned int rtcclkctrl; /* offset 0x0 */ 232 unsigned int clkstctrl; /* offset 0x4 */ 233 }; 234 235 /* Watchdog timer registers */ 236 struct wd_timer { 237 unsigned int resv1[4]; 238 unsigned int wdtwdsc; /* offset 0x010 */ 239 unsigned int wdtwdst; /* offset 0x014 */ 240 unsigned int wdtwisr; /* offset 0x018 */ 241 unsigned int wdtwier; /* offset 0x01C */ 242 unsigned int wdtwwer; /* offset 0x020 */ 243 unsigned int wdtwclr; /* offset 0x024 */ 244 unsigned int wdtwcrr; /* offset 0x028 */ 245 unsigned int wdtwldr; /* offset 0x02C */ 246 unsigned int wdtwtgr; /* offset 0x030 */ 247 unsigned int wdtwwps; /* offset 0x034 */ 248 unsigned int resv2[3]; 249 unsigned int wdtwdly; /* offset 0x044 */ 250 unsigned int wdtwspr; /* offset 0x048 */ 251 unsigned int resv3[1]; 252 unsigned int wdtwqeoi; /* offset 0x050 */ 253 unsigned int wdtwqstar; /* offset 0x054 */ 254 unsigned int wdtwqsta; /* offset 0x058 */ 255 unsigned int wdtwqens; /* offset 0x05C */ 256 unsigned int wdtwqenc; /* offset 0x060 */ 257 unsigned int resv4[39]; 258 unsigned int wdt_unfr; /* offset 0x100 */ 259 }; 260 261 /* Timer 32 bit registers */ 262 struct gptimer { 263 unsigned int tidr; /* offset 0x00 */ 264 unsigned char res1[12]; 265 unsigned int tiocp_cfg; /* offset 0x10 */ 266 unsigned char res2[12]; 267 unsigned int tier; /* offset 0x20 */ 268 unsigned int tistatr; /* offset 0x24 */ 269 unsigned int tistat; /* offset 0x28 */ 270 unsigned int tisr; /* offset 0x2c */ 271 unsigned int tcicr; /* offset 0x30 */ 272 unsigned int twer; /* offset 0x34 */ 273 unsigned int tclr; /* offset 0x38 */ 274 unsigned int tcrr; /* offset 0x3c */ 275 unsigned int tldr; /* offset 0x40 */ 276 unsigned int ttgr; /* offset 0x44 */ 277 unsigned int twpc; /* offset 0x48 */ 278 unsigned int tmar; /* offset 0x4c */ 279 unsigned int tcar1; /* offset 0x50 */ 280 unsigned int tscir; /* offset 0x54 */ 281 unsigned int tcar2; /* offset 0x58 */ 282 }; 283 284 /* RTC Registers */ 285 struct rtc_regs { 286 unsigned int res[21]; 287 unsigned int osc; /* offset 0x54 */ 288 unsigned int res2[5]; 289 unsigned int kick0r; /* offset 0x6c */ 290 unsigned int kick1r; /* offset 0x70 */ 291 }; 292 293 /* UART Registers */ 294 struct uart_sys { 295 unsigned int resv1[21]; 296 unsigned int uartsyscfg; /* offset 0x54 */ 297 unsigned int uartsyssts; /* offset 0x58 */ 298 }; 299 300 /* VTP Registers */ 301 struct vtp_reg { 302 unsigned int vtp0ctrlreg; 303 }; 304 305 /* Control Status Register */ 306 struct ctrl_stat { 307 unsigned int resv1[16]; 308 unsigned int statusreg; /* ofset 0x40 */ 309 unsigned int resv2[51]; 310 unsigned int secure_emif_sdram_config; /* offset 0x0110 */ 311 }; 312 313 /* AM33XX GPIO registers */ 314 #define OMAP_GPIO_REVISION 0x0000 315 #define OMAP_GPIO_SYSCONFIG 0x0010 316 #define OMAP_GPIO_SYSSTATUS 0x0114 317 #define OMAP_GPIO_IRQSTATUS1 0x002c 318 #define OMAP_GPIO_IRQSTATUS2 0x0030 319 #define OMAP_GPIO_CTRL 0x0130 320 #define OMAP_GPIO_OE 0x0134 321 #define OMAP_GPIO_DATAIN 0x0138 322 #define OMAP_GPIO_DATAOUT 0x013c 323 #define OMAP_GPIO_LEVELDETECT0 0x0140 324 #define OMAP_GPIO_LEVELDETECT1 0x0144 325 #define OMAP_GPIO_RISINGDETECT 0x0148 326 #define OMAP_GPIO_FALLINGDETECT 0x014c 327 #define OMAP_GPIO_DEBOUNCE_EN 0x0150 328 #define OMAP_GPIO_DEBOUNCE_VAL 0x0154 329 #define OMAP_GPIO_CLEARDATAOUT 0x0190 330 #define OMAP_GPIO_SETDATAOUT 0x0194 331 332 /* Control Device Register */ 333 struct ctrl_dev { 334 unsigned int deviceid; /* offset 0x00 */ 335 unsigned int resv1[7]; 336 unsigned int usb_ctrl0; /* offset 0x20 */ 337 unsigned int resv2; 338 unsigned int usb_ctrl1; /* offset 0x28 */ 339 unsigned int resv3; 340 unsigned int macid0l; /* offset 0x30 */ 341 unsigned int macid0h; /* offset 0x34 */ 342 unsigned int macid1l; /* offset 0x38 */ 343 unsigned int macid1h; /* offset 0x3c */ 344 unsigned int resv4[4]; 345 unsigned int miisel; /* offset 0x50 */ 346 }; 347 #endif /* __ASSEMBLY__ */ 348 #endif /* __KERNEL_STRICT_NAMES */ 349 350 #endif /* _AM33XX_CPU_H */ 351