1 /* 2 * cpu.h 3 * 4 * AM33xx specific header file 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _AM33XX_CPU_H 12 #define _AM33XX_CPU_H 13 14 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 15 #include <asm/types.h> 16 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 17 18 #include <asm/arch/hardware.h> 19 20 #define BIT(x) (1 << x) 21 #define CL_BIT(x) (0 << x) 22 23 /* Timer register bits */ 24 #define TCLR_ST BIT(0) /* Start=1 Stop=0 */ 25 #define TCLR_AR BIT(1) /* Auto reload */ 26 #define TCLR_PRE BIT(5) /* Pre-scaler enable */ 27 #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */ 28 #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */ 29 30 /* device type */ 31 #define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) 32 #define TST_DEVICE 0x0 33 #define EMU_DEVICE 0x1 34 #define HS_DEVICE 0x2 35 #define GP_DEVICE 0x3 36 37 /* cpu-id for AM33XX and TI81XX family */ 38 #define AM335X 0xB944 39 #define TI81XX 0xB81E 40 #define DEVICE_ID (CTRL_BASE + 0x0600) 41 #define DEVICE_ID_MASK 0x1FFF 42 43 /* MPU max frequencies */ 44 #define AM335X_ZCZ_300 0x1FEF 45 #define AM335X_ZCZ_600 0x1FAF 46 #define AM335X_ZCZ_720 0x1F2F 47 #define AM335X_ZCZ_800 0x1E2F 48 #define AM335X_ZCZ_1000 0x1C2F 49 #define AM335X_ZCE_300 0x1FDF 50 #define AM335X_ZCE_600 0x1F9F 51 52 /* This gives the status of the boot mode pins on the evm */ 53 #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ 54 | BIT(3) | BIT(4)) 55 56 #define PRM_RSTCTRL_RESET 0x01 57 #define PRM_RSTST_WARM_RESET_MASK 0x232 58 59 /* 60 * Watchdog: 61 * Using the prescaler, the OMAP watchdog could go for many 62 * months before firing. These limits work without scaling, 63 * with the 60 second default assumed by most tools and docs. 64 */ 65 #define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */ 66 #define TIMER_MARGIN_DEFAULT 60 /* 60 secs */ 67 #define TIMER_MARGIN_MIN 1 68 69 #define PTV 0 /* prescale */ 70 #define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1) 71 #define WDT_WWPS_PEND_WCLR BIT(0) 72 #define WDT_WWPS_PEND_WLDR BIT(2) 73 #define WDT_WWPS_PEND_WTGR BIT(3) 74 #define WDT_WWPS_PEND_WSPR BIT(4) 75 76 #define WDT_WCLR_PRE BIT(5) 77 #define WDT_WCLR_PTV_OFF 2 78 79 #ifndef __KERNEL_STRICT_NAMES 80 #ifndef __ASSEMBLY__ 81 struct gpmc_cs { 82 u32 config1; /* 0x00 */ 83 u32 config2; /* 0x04 */ 84 u32 config3; /* 0x08 */ 85 u32 config4; /* 0x0C */ 86 u32 config5; /* 0x10 */ 87 u32 config6; /* 0x14 */ 88 u32 config7; /* 0x18 */ 89 u32 nand_cmd; /* 0x1C */ 90 u32 nand_adr; /* 0x20 */ 91 u32 nand_dat; /* 0x24 */ 92 u8 res[8]; /* blow up to 0x30 byte */ 93 }; 94 95 struct bch_res_0_3 { 96 u32 bch_result_x[4]; 97 }; 98 99 struct gpmc { 100 u8 res1[0x10]; 101 u32 sysconfig; /* 0x10 */ 102 u8 res2[0x4]; 103 u32 irqstatus; /* 0x18 */ 104 u32 irqenable; /* 0x1C */ 105 u8 res3[0x20]; 106 u32 timeout_control; /* 0x40 */ 107 u8 res4[0xC]; 108 u32 config; /* 0x50 */ 109 u32 status; /* 0x54 */ 110 u8 res5[0x8]; /* 0x58 */ 111 struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ 112 u8 res6[0x14]; /* 0x1E0 */ 113 u32 ecc_config; /* 0x1F4 */ 114 u32 ecc_control; /* 0x1F8 */ 115 u32 ecc_size_config; /* 0x1FC */ 116 u32 ecc1_result; /* 0x200 */ 117 u32 ecc2_result; /* 0x204 */ 118 u32 ecc3_result; /* 0x208 */ 119 u32 ecc4_result; /* 0x20C */ 120 u32 ecc5_result; /* 0x210 */ 121 u32 ecc6_result; /* 0x214 */ 122 u32 ecc7_result; /* 0x218 */ 123 u32 ecc8_result; /* 0x21C */ 124 u32 ecc9_result; /* 0x220 */ 125 u8 res7[12]; /* 0x224 */ 126 u32 testmomde_ctrl; /* 0x230 */ 127 u8 res8[12]; /* 0x234 */ 128 struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */ 129 }; 130 131 /* Used for board specific gpmc initialization */ 132 extern struct gpmc *gpmc_cfg; 133 134 #ifndef CONFIG_AM43XX 135 /* Encapsulating core pll registers */ 136 struct cm_wkuppll { 137 unsigned int wkclkstctrl; /* offset 0x00 */ 138 unsigned int wkctrlclkctrl; /* offset 0x04 */ 139 unsigned int wkgpio0clkctrl; /* offset 0x08 */ 140 unsigned int wkl4wkclkctrl; /* offset 0x0c */ 141 unsigned int resv2[4]; 142 unsigned int idlestdpllmpu; /* offset 0x20 */ 143 unsigned int resv3[2]; 144 unsigned int clkseldpllmpu; /* offset 0x2c */ 145 unsigned int resv4[1]; 146 unsigned int idlestdpllddr; /* offset 0x34 */ 147 unsigned int resv5[2]; 148 unsigned int clkseldpllddr; /* offset 0x40 */ 149 unsigned int resv6[4]; 150 unsigned int clkseldplldisp; /* offset 0x54 */ 151 unsigned int resv7[1]; 152 unsigned int idlestdpllcore; /* offset 0x5c */ 153 unsigned int resv8[2]; 154 unsigned int clkseldpllcore; /* offset 0x68 */ 155 unsigned int resv9[1]; 156 unsigned int idlestdpllper; /* offset 0x70 */ 157 unsigned int resv10[2]; 158 unsigned int clkdcoldodpllper; /* offset 0x7c */ 159 unsigned int divm4dpllcore; /* offset 0x80 */ 160 unsigned int divm5dpllcore; /* offset 0x84 */ 161 unsigned int clkmoddpllmpu; /* offset 0x88 */ 162 unsigned int clkmoddpllper; /* offset 0x8c */ 163 unsigned int clkmoddpllcore; /* offset 0x90 */ 164 unsigned int clkmoddpllddr; /* offset 0x94 */ 165 unsigned int clkmoddplldisp; /* offset 0x98 */ 166 unsigned int clkseldpllper; /* offset 0x9c */ 167 unsigned int divm2dpllddr; /* offset 0xA0 */ 168 unsigned int divm2dplldisp; /* offset 0xA4 */ 169 unsigned int divm2dpllmpu; /* offset 0xA8 */ 170 unsigned int divm2dpllper; /* offset 0xAC */ 171 unsigned int resv11[1]; 172 unsigned int wkup_uart0ctrl; /* offset 0xB4 */ 173 unsigned int wkup_i2c0ctrl; /* offset 0xB8 */ 174 unsigned int resv12[7]; 175 unsigned int divm6dpllcore; /* offset 0xD8 */ 176 }; 177 178 /** 179 * Encapsulating peripheral functional clocks 180 * pll registers 181 */ 182 struct cm_perpll { 183 unsigned int l4lsclkstctrl; /* offset 0x00 */ 184 unsigned int l3sclkstctrl; /* offset 0x04 */ 185 unsigned int l4fwclkstctrl; /* offset 0x08 */ 186 unsigned int l3clkstctrl; /* offset 0x0c */ 187 unsigned int resv1; 188 unsigned int cpgmac0clkctrl; /* offset 0x14 */ 189 unsigned int lcdclkctrl; /* offset 0x18 */ 190 unsigned int usb0clkctrl; /* offset 0x1C */ 191 unsigned int resv2; 192 unsigned int tptc0clkctrl; /* offset 0x24 */ 193 unsigned int emifclkctrl; /* offset 0x28 */ 194 unsigned int ocmcramclkctrl; /* offset 0x2c */ 195 unsigned int gpmcclkctrl; /* offset 0x30 */ 196 unsigned int mcasp0clkctrl; /* offset 0x34 */ 197 unsigned int uart5clkctrl; /* offset 0x38 */ 198 unsigned int mmc0clkctrl; /* offset 0x3C */ 199 unsigned int elmclkctrl; /* offset 0x40 */ 200 unsigned int i2c2clkctrl; /* offset 0x44 */ 201 unsigned int i2c1clkctrl; /* offset 0x48 */ 202 unsigned int spi0clkctrl; /* offset 0x4C */ 203 unsigned int spi1clkctrl; /* offset 0x50 */ 204 unsigned int resv3[3]; 205 unsigned int l4lsclkctrl; /* offset 0x60 */ 206 unsigned int l4fwclkctrl; /* offset 0x64 */ 207 unsigned int mcasp1clkctrl; /* offset 0x68 */ 208 unsigned int uart1clkctrl; /* offset 0x6C */ 209 unsigned int uart2clkctrl; /* offset 0x70 */ 210 unsigned int uart3clkctrl; /* offset 0x74 */ 211 unsigned int uart4clkctrl; /* offset 0x78 */ 212 unsigned int timer7clkctrl; /* offset 0x7C */ 213 unsigned int timer2clkctrl; /* offset 0x80 */ 214 unsigned int timer3clkctrl; /* offset 0x84 */ 215 unsigned int timer4clkctrl; /* offset 0x88 */ 216 unsigned int resv4[8]; 217 unsigned int gpio1clkctrl; /* offset 0xAC */ 218 unsigned int gpio2clkctrl; /* offset 0xB0 */ 219 unsigned int gpio3clkctrl; /* offset 0xB4 */ 220 unsigned int resv5; 221 unsigned int tpccclkctrl; /* offset 0xBC */ 222 unsigned int dcan0clkctrl; /* offset 0xC0 */ 223 unsigned int dcan1clkctrl; /* offset 0xC4 */ 224 unsigned int resv6[2]; 225 unsigned int emiffwclkctrl; /* offset 0xD0 */ 226 unsigned int epwmss0clkctrl; /* offset 0xD4 */ 227 unsigned int epwmss2clkctrl; /* offset 0xD8 */ 228 unsigned int l3instrclkctrl; /* offset 0xDC */ 229 unsigned int l3clkctrl; /* Offset 0xE0 */ 230 unsigned int resv8[4]; 231 unsigned int mmc1clkctrl; /* offset 0xF4 */ 232 unsigned int mmc2clkctrl; /* offset 0xF8 */ 233 unsigned int resv9[8]; 234 unsigned int l4hsclkstctrl; /* offset 0x11C */ 235 unsigned int l4hsclkctrl; /* offset 0x120 */ 236 unsigned int resv10[8]; 237 unsigned int cpswclkstctrl; /* offset 0x144 */ 238 unsigned int lcdcclkstctrl; /* offset 0x148 */ 239 }; 240 #else 241 /* Encapsulating core pll registers */ 242 struct cm_wkuppll { 243 unsigned int resv0[136]; 244 unsigned int wkl4wkclkctrl; /* offset 0x220 */ 245 unsigned int resv1[55]; 246 unsigned int wkclkstctrl; /* offset 0x300 */ 247 unsigned int resv2[15]; 248 unsigned int wkup_i2c0ctrl; /* offset 0x340 */ 249 unsigned int resv3; 250 unsigned int wkup_uart0ctrl; /* offset 0x348 */ 251 unsigned int resv4[5]; 252 unsigned int wkctrlclkctrl; /* offset 0x360 */ 253 unsigned int resv5; 254 unsigned int wkgpio0clkctrl; /* offset 0x368 */ 255 256 unsigned int resv6[109]; 257 unsigned int clkmoddpllcore; /* offset 0x520 */ 258 unsigned int idlestdpllcore; /* offset 0x524 */ 259 unsigned int resv61; 260 unsigned int clkseldpllcore; /* offset 0x52C */ 261 unsigned int resv7[2]; 262 unsigned int divm4dpllcore; /* offset 0x538 */ 263 unsigned int divm5dpllcore; /* offset 0x53C */ 264 unsigned int divm6dpllcore; /* offset 0x540 */ 265 266 unsigned int resv8[7]; 267 unsigned int clkmoddpllmpu; /* offset 0x560 */ 268 unsigned int idlestdpllmpu; /* offset 0x564 */ 269 unsigned int resv9; 270 unsigned int clkseldpllmpu; /* offset 0x56c */ 271 unsigned int divm2dpllmpu; /* offset 0x570 */ 272 273 unsigned int resv10[11]; 274 unsigned int clkmoddpllddr; /* offset 0x5A0 */ 275 unsigned int idlestdpllddr; /* offset 0x5A4 */ 276 unsigned int resv11; 277 unsigned int clkseldpllddr; /* offset 0x5AC */ 278 unsigned int divm2dpllddr; /* offset 0x5B0 */ 279 280 unsigned int resv12[11]; 281 unsigned int clkmoddpllper; /* offset 0x5E0 */ 282 unsigned int idlestdpllper; /* offset 0x5E4 */ 283 unsigned int resv13; 284 unsigned int clkseldpllper; /* offset 0x5EC */ 285 unsigned int divm2dpllper; /* offset 0x5F0 */ 286 unsigned int resv14[8]; 287 unsigned int clkdcoldodpllper; /* offset 0x614 */ 288 289 unsigned int resv15[2]; 290 unsigned int clkmoddplldisp; /* offset 0x620 */ 291 unsigned int resv16[2]; 292 unsigned int clkseldplldisp; /* offset 0x62C */ 293 unsigned int divm2dplldisp; /* offset 0x630 */ 294 }; 295 296 /* 297 * Encapsulating peripheral functional clocks 298 * pll registers 299 */ 300 struct cm_perpll { 301 unsigned int l3clkstctrl; /* offset 0x00 */ 302 unsigned int resv0[7]; 303 unsigned int l3clkctrl; /* Offset 0x20 */ 304 unsigned int resv1[7]; 305 unsigned int l3instrclkctrl; /* offset 0x40 */ 306 unsigned int resv2[3]; 307 unsigned int ocmcramclkctrl; /* offset 0x50 */ 308 unsigned int resv3[9]; 309 unsigned int tpccclkctrl; /* offset 0x78 */ 310 unsigned int resv4; 311 unsigned int tptc0clkctrl; /* offset 0x80 */ 312 313 unsigned int resv5[7]; 314 unsigned int l4hsclkctrl; /* offset 0x0A0 */ 315 unsigned int resv6; 316 unsigned int l4fwclkctrl; /* offset 0x0A8 */ 317 unsigned int resv7[85]; 318 unsigned int l3sclkstctrl; /* offset 0x200 */ 319 unsigned int resv8[7]; 320 unsigned int gpmcclkctrl; /* offset 0x220 */ 321 unsigned int resv9[5]; 322 unsigned int mcasp0clkctrl; /* offset 0x238 */ 323 unsigned int resv10; 324 unsigned int mcasp1clkctrl; /* offset 0x240 */ 325 unsigned int resv11; 326 unsigned int mmc2clkctrl; /* offset 0x248 */ 327 unsigned int resv12[5]; 328 unsigned int usb0clkctrl; /* offset 0x260 */ 329 unsigned int resv13[103]; 330 unsigned int l4lsclkstctrl; /* offset 0x400 */ 331 unsigned int resv14[7]; 332 unsigned int l4lsclkctrl; /* offset 0x420 */ 333 unsigned int resv15; 334 unsigned int dcan0clkctrl; /* offset 0x428 */ 335 unsigned int resv16; 336 unsigned int dcan1clkctrl; /* offset 0x430 */ 337 unsigned int resv17[13]; 338 unsigned int elmclkctrl; /* offset 0x468 */ 339 340 unsigned int resv18[3]; 341 unsigned int gpio1clkctrl; /* offset 0x478 */ 342 unsigned int resv19; 343 unsigned int gpio2clkctrl; /* offset 0x480 */ 344 unsigned int resv20; 345 unsigned int gpio3clkctrl; /* offset 0x488 */ 346 unsigned int resv21[7]; 347 348 unsigned int i2c1clkctrl; /* offset 0x4A8 */ 349 unsigned int resv22; 350 unsigned int i2c2clkctrl; /* offset 0x4B0 */ 351 unsigned int resv23[3]; 352 unsigned int mmc0clkctrl; /* offset 0x4C0 */ 353 unsigned int resv24; 354 unsigned int mmc1clkctrl; /* offset 0x4C8 */ 355 356 unsigned int resv25[13]; 357 unsigned int spi0clkctrl; /* offset 0x500 */ 358 unsigned int resv26; 359 unsigned int spi1clkctrl; /* offset 0x508 */ 360 unsigned int resv27[9]; 361 unsigned int timer2clkctrl; /* offset 0x530 */ 362 unsigned int resv28; 363 unsigned int timer3clkctrl; /* offset 0x538 */ 364 unsigned int resv29; 365 unsigned int timer4clkctrl; /* offset 0x540 */ 366 unsigned int resv30[5]; 367 unsigned int timer7clkctrl; /* offset 0x558 */ 368 369 unsigned int resv31[9]; 370 unsigned int uart1clkctrl; /* offset 0x580 */ 371 unsigned int resv32; 372 unsigned int uart2clkctrl; /* offset 0x588 */ 373 unsigned int resv33; 374 unsigned int uart3clkctrl; /* offset 0x590 */ 375 unsigned int resv34; 376 unsigned int uart4clkctrl; /* offset 0x598 */ 377 unsigned int resv35; 378 unsigned int uart5clkctrl; /* offset 0x5A0 */ 379 unsigned int resv36[87]; 380 381 unsigned int emifclkstctrl; /* offset 0x700 */ 382 unsigned int resv361[7]; 383 unsigned int emifclkctrl; /* offset 0x720 */ 384 unsigned int resv37[3]; 385 unsigned int emiffwclkctrl; /* offset 0x730 */ 386 unsigned int resv371; 387 unsigned int otfaemifclkctrl; /* offset 0x738 */ 388 unsigned int resv38[57]; 389 unsigned int lcdclkctrl; /* offset 0x820 */ 390 unsigned int resv39[183]; 391 unsigned int cpswclkstctrl; /* offset 0xB00 */ 392 unsigned int resv40[7]; 393 unsigned int cpgmac0clkctrl; /* offset 0xB20 */ 394 }; 395 #endif /* CONFIG_AM43XX */ 396 397 /* Encapsulating Display pll registers */ 398 struct cm_dpll { 399 unsigned int resv1[2]; 400 unsigned int clktimer2clk; /* offset 0x08 */ 401 unsigned int resv2[10]; 402 unsigned int clklcdcpixelclk; /* offset 0x34 */ 403 }; 404 405 /* Control Module RTC registers */ 406 struct cm_rtc { 407 unsigned int rtcclkctrl; /* offset 0x0 */ 408 unsigned int clkstctrl; /* offset 0x4 */ 409 }; 410 411 /* Watchdog timer registers */ 412 struct wd_timer { 413 unsigned int resv1[4]; 414 unsigned int wdtwdsc; /* offset 0x010 */ 415 unsigned int wdtwdst; /* offset 0x014 */ 416 unsigned int wdtwisr; /* offset 0x018 */ 417 unsigned int wdtwier; /* offset 0x01C */ 418 unsigned int wdtwwer; /* offset 0x020 */ 419 unsigned int wdtwclr; /* offset 0x024 */ 420 unsigned int wdtwcrr; /* offset 0x028 */ 421 unsigned int wdtwldr; /* offset 0x02C */ 422 unsigned int wdtwtgr; /* offset 0x030 */ 423 unsigned int wdtwwps; /* offset 0x034 */ 424 unsigned int resv2[3]; 425 unsigned int wdtwdly; /* offset 0x044 */ 426 unsigned int wdtwspr; /* offset 0x048 */ 427 unsigned int resv3[1]; 428 unsigned int wdtwqeoi; /* offset 0x050 */ 429 unsigned int wdtwqstar; /* offset 0x054 */ 430 unsigned int wdtwqsta; /* offset 0x058 */ 431 unsigned int wdtwqens; /* offset 0x05C */ 432 unsigned int wdtwqenc; /* offset 0x060 */ 433 unsigned int resv4[39]; 434 unsigned int wdt_unfr; /* offset 0x100 */ 435 }; 436 437 /* Timer 32 bit registers */ 438 struct gptimer { 439 unsigned int tidr; /* offset 0x00 */ 440 unsigned char res1[12]; 441 unsigned int tiocp_cfg; /* offset 0x10 */ 442 unsigned char res2[12]; 443 unsigned int tier; /* offset 0x20 */ 444 unsigned int tistatr; /* offset 0x24 */ 445 unsigned int tistat; /* offset 0x28 */ 446 unsigned int tisr; /* offset 0x2c */ 447 unsigned int tcicr; /* offset 0x30 */ 448 unsigned int twer; /* offset 0x34 */ 449 unsigned int tclr; /* offset 0x38 */ 450 unsigned int tcrr; /* offset 0x3c */ 451 unsigned int tldr; /* offset 0x40 */ 452 unsigned int ttgr; /* offset 0x44 */ 453 unsigned int twpc; /* offset 0x48 */ 454 unsigned int tmar; /* offset 0x4c */ 455 unsigned int tcar1; /* offset 0x50 */ 456 unsigned int tscir; /* offset 0x54 */ 457 unsigned int tcar2; /* offset 0x58 */ 458 }; 459 460 /* RTC Registers */ 461 struct rtc_regs { 462 unsigned int res[21]; 463 unsigned int osc; /* offset 0x54 */ 464 unsigned int res2[5]; 465 unsigned int kick0r; /* offset 0x6c */ 466 unsigned int kick1r; /* offset 0x70 */ 467 }; 468 469 /* UART Registers */ 470 struct uart_sys { 471 unsigned int resv1[21]; 472 unsigned int uartsyscfg; /* offset 0x54 */ 473 unsigned int uartsyssts; /* offset 0x58 */ 474 }; 475 476 /* VTP Registers */ 477 struct vtp_reg { 478 unsigned int vtp0ctrlreg; 479 }; 480 481 /* Control Status Register */ 482 struct ctrl_stat { 483 unsigned int resv1[16]; 484 unsigned int statusreg; /* ofset 0x40 */ 485 unsigned int resv2[51]; 486 unsigned int secure_emif_sdram_config; /* offset 0x0110 */ 487 }; 488 489 /* AM33XX GPIO registers */ 490 #define OMAP_GPIO_REVISION 0x0000 491 #define OMAP_GPIO_SYSCONFIG 0x0010 492 #define OMAP_GPIO_SYSSTATUS 0x0114 493 #define OMAP_GPIO_IRQSTATUS1 0x002c 494 #define OMAP_GPIO_IRQSTATUS2 0x0030 495 #define OMAP_GPIO_CTRL 0x0130 496 #define OMAP_GPIO_OE 0x0134 497 #define OMAP_GPIO_DATAIN 0x0138 498 #define OMAP_GPIO_DATAOUT 0x013c 499 #define OMAP_GPIO_LEVELDETECT0 0x0140 500 #define OMAP_GPIO_LEVELDETECT1 0x0144 501 #define OMAP_GPIO_RISINGDETECT 0x0148 502 #define OMAP_GPIO_FALLINGDETECT 0x014c 503 #define OMAP_GPIO_DEBOUNCE_EN 0x0150 504 #define OMAP_GPIO_DEBOUNCE_VAL 0x0154 505 #define OMAP_GPIO_CLEARDATAOUT 0x0190 506 #define OMAP_GPIO_SETDATAOUT 0x0194 507 508 /* Control Device Register */ 509 struct ctrl_dev { 510 unsigned int deviceid; /* offset 0x00 */ 511 unsigned int resv1[7]; 512 unsigned int usb_ctrl0; /* offset 0x20 */ 513 unsigned int resv2; 514 unsigned int usb_ctrl1; /* offset 0x28 */ 515 unsigned int resv3; 516 unsigned int macid0l; /* offset 0x30 */ 517 unsigned int macid0h; /* offset 0x34 */ 518 unsigned int macid1l; /* offset 0x38 */ 519 unsigned int macid1h; /* offset 0x3c */ 520 unsigned int resv4[4]; 521 unsigned int miisel; /* offset 0x50 */ 522 unsigned int resv5[106]; 523 unsigned int efuse_sma; /* offset 0x1FC */ 524 }; 525 526 /* gmii_sel register defines */ 527 #define GMII1_SEL_MII 0x0 528 #define GMII1_SEL_RMII 0x1 529 #define GMII1_SEL_RGMII 0x2 530 #define GMII2_SEL_MII 0x0 531 #define GMII2_SEL_RMII 0x4 532 #define GMII2_SEL_RGMII 0x8 533 #define RGMII1_IDMODE BIT(4) 534 #define RGMII2_IDMODE BIT(5) 535 #define RMII1_IO_CLK_EN BIT(6) 536 #define RMII2_IO_CLK_EN BIT(7) 537 538 #define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII) 539 #define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII) 540 #define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII) 541 #define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE) 542 #define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN) 543 544 /* PWMSS */ 545 struct pwmss_regs { 546 unsigned int idver; 547 unsigned int sysconfig; 548 unsigned int clkconfig; 549 unsigned int clkstatus; 550 }; 551 #define ECAP_CLK_EN BIT(0) 552 #define ECAP_CLK_STOP_REQ BIT(1) 553 554 struct pwmss_ecap_regs { 555 unsigned int tsctr; 556 unsigned int ctrphs; 557 unsigned int cap1; 558 unsigned int cap2; 559 unsigned int cap3; 560 unsigned int cap4; 561 unsigned int resv1[4]; 562 unsigned short ecctl1; 563 unsigned short ecctl2; 564 }; 565 566 /* Capture Control register 2 */ 567 #define ECTRL2_SYNCOSEL_MASK (0x03 << 6) 568 #define ECTRL2_MDSL_ECAP BIT(9) 569 #define ECTRL2_CTRSTP_FREERUN BIT(4) 570 #define ECTRL2_PLSL_LOW BIT(10) 571 #define ECTRL2_SYNC_EN BIT(5) 572 573 #endif /* __ASSEMBLY__ */ 574 #endif /* __KERNEL_STRICT_NAMES */ 575 576 #endif /* _AM33XX_CPU_H */ 577