1 /* 2 * cpu.h 3 * 4 * AM33xx specific header file 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _AM33XX_CPU_H 12 #define _AM33XX_CPU_H 13 14 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 15 #include <asm/types.h> 16 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 17 18 #include <asm/arch/hardware.h> 19 20 #define BIT(x) (1 << x) 21 #define CL_BIT(x) (0 << x) 22 23 /* Timer register bits */ 24 #define TCLR_ST BIT(0) /* Start=1 Stop=0 */ 25 #define TCLR_AR BIT(1) /* Auto reload */ 26 #define TCLR_PRE BIT(5) /* Pre-scaler enable */ 27 #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */ 28 #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */ 29 30 /* device type */ 31 #define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) 32 #define TST_DEVICE 0x0 33 #define EMU_DEVICE 0x1 34 #define HS_DEVICE 0x2 35 #define GP_DEVICE 0x3 36 37 /* cpu-id for AM33XX and TI81XX family */ 38 #define AM335X 0xB944 39 #define TI81XX 0xB81E 40 #define DEVICE_ID (CTRL_BASE + 0x0600) 41 42 /* This gives the status of the boot mode pins on the evm */ 43 #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ 44 | BIT(3) | BIT(4)) 45 46 #define PRM_RSTCTRL_RESET 0x01 47 #define PRM_RSTST_WARM_RESET_MASK 0x232 48 49 #ifndef __KERNEL_STRICT_NAMES 50 #ifndef __ASSEMBLY__ 51 struct gpmc_cs { 52 u32 config1; /* 0x00 */ 53 u32 config2; /* 0x04 */ 54 u32 config3; /* 0x08 */ 55 u32 config4; /* 0x0C */ 56 u32 config5; /* 0x10 */ 57 u32 config6; /* 0x14 */ 58 u32 config7; /* 0x18 */ 59 u32 nand_cmd; /* 0x1C */ 60 u32 nand_adr; /* 0x20 */ 61 u32 nand_dat; /* 0x24 */ 62 u8 res[8]; /* blow up to 0x30 byte */ 63 }; 64 65 struct bch_res_0_3 { 66 u32 bch_result_x[4]; 67 }; 68 69 struct gpmc { 70 u8 res1[0x10]; 71 u32 sysconfig; /* 0x10 */ 72 u8 res2[0x4]; 73 u32 irqstatus; /* 0x18 */ 74 u32 irqenable; /* 0x1C */ 75 u8 res3[0x20]; 76 u32 timeout_control; /* 0x40 */ 77 u8 res4[0xC]; 78 u32 config; /* 0x50 */ 79 u32 status; /* 0x54 */ 80 u8 res5[0x8]; /* 0x58 */ 81 struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ 82 u8 res6[0x14]; /* 0x1E0 */ 83 u32 ecc_config; /* 0x1F4 */ 84 u32 ecc_control; /* 0x1F8 */ 85 u32 ecc_size_config; /* 0x1FC */ 86 u32 ecc1_result; /* 0x200 */ 87 u32 ecc2_result; /* 0x204 */ 88 u32 ecc3_result; /* 0x208 */ 89 u32 ecc4_result; /* 0x20C */ 90 u32 ecc5_result; /* 0x210 */ 91 u32 ecc6_result; /* 0x214 */ 92 u32 ecc7_result; /* 0x218 */ 93 u32 ecc8_result; /* 0x21C */ 94 u32 ecc9_result; /* 0x220 */ 95 u8 res7[12]; /* 0x224 */ 96 u32 testmomde_ctrl; /* 0x230 */ 97 u8 res8[12]; /* 0x234 */ 98 struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */ 99 }; 100 101 /* Used for board specific gpmc initialization */ 102 extern struct gpmc *gpmc_cfg; 103 104 #ifndef CONFIG_AM43XX 105 /* Encapsulating core pll registers */ 106 struct cm_wkuppll { 107 unsigned int wkclkstctrl; /* offset 0x00 */ 108 unsigned int wkctrlclkctrl; /* offset 0x04 */ 109 unsigned int wkgpio0clkctrl; /* offset 0x08 */ 110 unsigned int wkl4wkclkctrl; /* offset 0x0c */ 111 unsigned int resv2[4]; 112 unsigned int idlestdpllmpu; /* offset 0x20 */ 113 unsigned int resv3[2]; 114 unsigned int clkseldpllmpu; /* offset 0x2c */ 115 unsigned int resv4[1]; 116 unsigned int idlestdpllddr; /* offset 0x34 */ 117 unsigned int resv5[2]; 118 unsigned int clkseldpllddr; /* offset 0x40 */ 119 unsigned int resv6[4]; 120 unsigned int clkseldplldisp; /* offset 0x54 */ 121 unsigned int resv7[1]; 122 unsigned int idlestdpllcore; /* offset 0x5c */ 123 unsigned int resv8[2]; 124 unsigned int clkseldpllcore; /* offset 0x68 */ 125 unsigned int resv9[1]; 126 unsigned int idlestdpllper; /* offset 0x70 */ 127 unsigned int resv10[2]; 128 unsigned int clkdcoldodpllper; /* offset 0x7c */ 129 unsigned int divm4dpllcore; /* offset 0x80 */ 130 unsigned int divm5dpllcore; /* offset 0x84 */ 131 unsigned int clkmoddpllmpu; /* offset 0x88 */ 132 unsigned int clkmoddpllper; /* offset 0x8c */ 133 unsigned int clkmoddpllcore; /* offset 0x90 */ 134 unsigned int clkmoddpllddr; /* offset 0x94 */ 135 unsigned int clkmoddplldisp; /* offset 0x98 */ 136 unsigned int clkseldpllper; /* offset 0x9c */ 137 unsigned int divm2dpllddr; /* offset 0xA0 */ 138 unsigned int divm2dplldisp; /* offset 0xA4 */ 139 unsigned int divm2dpllmpu; /* offset 0xA8 */ 140 unsigned int divm2dpllper; /* offset 0xAC */ 141 unsigned int resv11[1]; 142 unsigned int wkup_uart0ctrl; /* offset 0xB4 */ 143 unsigned int wkup_i2c0ctrl; /* offset 0xB8 */ 144 unsigned int resv12[7]; 145 unsigned int divm6dpllcore; /* offset 0xD8 */ 146 }; 147 148 /** 149 * Encapsulating peripheral functional clocks 150 * pll registers 151 */ 152 struct cm_perpll { 153 unsigned int l4lsclkstctrl; /* offset 0x00 */ 154 unsigned int l3sclkstctrl; /* offset 0x04 */ 155 unsigned int l4fwclkstctrl; /* offset 0x08 */ 156 unsigned int l3clkstctrl; /* offset 0x0c */ 157 unsigned int resv1; 158 unsigned int cpgmac0clkctrl; /* offset 0x14 */ 159 unsigned int lcdclkctrl; /* offset 0x18 */ 160 unsigned int usb0clkctrl; /* offset 0x1C */ 161 unsigned int resv2; 162 unsigned int tptc0clkctrl; /* offset 0x24 */ 163 unsigned int emifclkctrl; /* offset 0x28 */ 164 unsigned int ocmcramclkctrl; /* offset 0x2c */ 165 unsigned int gpmcclkctrl; /* offset 0x30 */ 166 unsigned int mcasp0clkctrl; /* offset 0x34 */ 167 unsigned int uart5clkctrl; /* offset 0x38 */ 168 unsigned int mmc0clkctrl; /* offset 0x3C */ 169 unsigned int elmclkctrl; /* offset 0x40 */ 170 unsigned int i2c2clkctrl; /* offset 0x44 */ 171 unsigned int i2c1clkctrl; /* offset 0x48 */ 172 unsigned int spi0clkctrl; /* offset 0x4C */ 173 unsigned int spi1clkctrl; /* offset 0x50 */ 174 unsigned int resv3[3]; 175 unsigned int l4lsclkctrl; /* offset 0x60 */ 176 unsigned int l4fwclkctrl; /* offset 0x64 */ 177 unsigned int mcasp1clkctrl; /* offset 0x68 */ 178 unsigned int uart1clkctrl; /* offset 0x6C */ 179 unsigned int uart2clkctrl; /* offset 0x70 */ 180 unsigned int uart3clkctrl; /* offset 0x74 */ 181 unsigned int uart4clkctrl; /* offset 0x78 */ 182 unsigned int timer7clkctrl; /* offset 0x7C */ 183 unsigned int timer2clkctrl; /* offset 0x80 */ 184 unsigned int timer3clkctrl; /* offset 0x84 */ 185 unsigned int timer4clkctrl; /* offset 0x88 */ 186 unsigned int resv4[8]; 187 unsigned int gpio1clkctrl; /* offset 0xAC */ 188 unsigned int gpio2clkctrl; /* offset 0xB0 */ 189 unsigned int gpio3clkctrl; /* offset 0xB4 */ 190 unsigned int resv5; 191 unsigned int tpccclkctrl; /* offset 0xBC */ 192 unsigned int dcan0clkctrl; /* offset 0xC0 */ 193 unsigned int dcan1clkctrl; /* offset 0xC4 */ 194 unsigned int resv6[2]; 195 unsigned int emiffwclkctrl; /* offset 0xD0 */ 196 unsigned int resv7[2]; 197 unsigned int l3instrclkctrl; /* offset 0xDC */ 198 unsigned int l3clkctrl; /* Offset 0xE0 */ 199 unsigned int resv8[4]; 200 unsigned int mmc1clkctrl; /* offset 0xF4 */ 201 unsigned int mmc2clkctrl; /* offset 0xF8 */ 202 unsigned int resv9[8]; 203 unsigned int l4hsclkstctrl; /* offset 0x11C */ 204 unsigned int l4hsclkctrl; /* offset 0x120 */ 205 unsigned int resv10[8]; 206 unsigned int cpswclkstctrl; /* offset 0x144 */ 207 }; 208 #else 209 /* Encapsulating core pll registers */ 210 struct cm_wkuppll { 211 unsigned int resv0[136]; 212 unsigned int wkl4wkclkctrl; /* offset 0x220 */ 213 unsigned int resv1[55]; 214 unsigned int wkclkstctrl; /* offset 0x300 */ 215 unsigned int resv2[15]; 216 unsigned int wkup_i2c0ctrl; /* offset 0x340 */ 217 unsigned int resv3; 218 unsigned int wkup_uart0ctrl; /* offset 0x348 */ 219 unsigned int resv4[5]; 220 unsigned int wkctrlclkctrl; /* offset 0x360 */ 221 unsigned int resv5; 222 unsigned int wkgpio0clkctrl; /* offset 0x368 */ 223 224 unsigned int resv6[109]; 225 unsigned int clkmoddpllcore; /* offset 0x520 */ 226 unsigned int idlestdpllcore; /* offset 0x524 */ 227 unsigned int resv61; 228 unsigned int clkseldpllcore; /* offset 0x52C */ 229 unsigned int resv7[2]; 230 unsigned int divm4dpllcore; /* offset 0x538 */ 231 unsigned int divm5dpllcore; /* offset 0x53C */ 232 unsigned int divm6dpllcore; /* offset 0x540 */ 233 234 unsigned int resv8[7]; 235 unsigned int clkmoddpllmpu; /* offset 0x560 */ 236 unsigned int idlestdpllmpu; /* offset 0x564 */ 237 unsigned int resv9; 238 unsigned int clkseldpllmpu; /* offset 0x56c */ 239 unsigned int divm2dpllmpu; /* offset 0x570 */ 240 241 unsigned int resv10[11]; 242 unsigned int clkmoddpllddr; /* offset 0x5A0 */ 243 unsigned int idlestdpllddr; /* offset 0x5A4 */ 244 unsigned int resv11; 245 unsigned int clkseldpllddr; /* offset 0x5AC */ 246 unsigned int divm2dpllddr; /* offset 0x5B0 */ 247 248 unsigned int resv12[11]; 249 unsigned int clkmoddpllper; /* offset 0x5E0 */ 250 unsigned int idlestdpllper; /* offset 0x5E4 */ 251 unsigned int resv13; 252 unsigned int clkseldpllper; /* offset 0x5EC */ 253 unsigned int divm2dpllper; /* offset 0x5F0 */ 254 unsigned int resv14[8]; 255 unsigned int clkdcoldodpllper; /* offset 0x614 */ 256 257 unsigned int resv15[2]; 258 unsigned int clkmoddplldisp; /* offset 0x620 */ 259 unsigned int resv16[2]; 260 unsigned int clkseldplldisp; /* offset 0x62C */ 261 unsigned int divm2dplldisp; /* offset 0x630 */ 262 }; 263 264 /* 265 * Encapsulating peripheral functional clocks 266 * pll registers 267 */ 268 struct cm_perpll { 269 unsigned int l3clkstctrl; /* offset 0x00 */ 270 unsigned int resv0[7]; 271 unsigned int l3clkctrl; /* Offset 0x20 */ 272 unsigned int resv1[7]; 273 unsigned int l3instrclkctrl; /* offset 0x40 */ 274 unsigned int resv2[3]; 275 unsigned int ocmcramclkctrl; /* offset 0x50 */ 276 unsigned int resv3[9]; 277 unsigned int tpccclkctrl; /* offset 0x78 */ 278 unsigned int resv4; 279 unsigned int tptc0clkctrl; /* offset 0x80 */ 280 281 unsigned int resv5[7]; 282 unsigned int l4hsclkctrl; /* offset 0x0A0 */ 283 unsigned int resv6; 284 unsigned int l4fwclkctrl; /* offset 0x0A8 */ 285 unsigned int resv7[85]; 286 unsigned int l3sclkstctrl; /* offset 0x200 */ 287 unsigned int resv8[7]; 288 unsigned int gpmcclkctrl; /* offset 0x220 */ 289 unsigned int resv9[5]; 290 unsigned int mcasp0clkctrl; /* offset 0x238 */ 291 unsigned int resv10; 292 unsigned int mcasp1clkctrl; /* offset 0x240 */ 293 unsigned int resv11; 294 unsigned int mmc2clkctrl; /* offset 0x248 */ 295 unsigned int resv12[5]; 296 unsigned int usb0clkctrl; /* offset 0x260 */ 297 unsigned int resv13[103]; 298 unsigned int l4lsclkstctrl; /* offset 0x400 */ 299 unsigned int resv14[7]; 300 unsigned int l4lsclkctrl; /* offset 0x420 */ 301 unsigned int resv15; 302 unsigned int dcan0clkctrl; /* offset 0x428 */ 303 unsigned int resv16; 304 unsigned int dcan1clkctrl; /* offset 0x430 */ 305 unsigned int resv17[13]; 306 unsigned int elmclkctrl; /* offset 0x468 */ 307 308 unsigned int resv18[3]; 309 unsigned int gpio1clkctrl; /* offset 0x478 */ 310 unsigned int resv19; 311 unsigned int gpio2clkctrl; /* offset 0x480 */ 312 unsigned int resv20; 313 unsigned int gpio3clkctrl; /* offset 0x488 */ 314 unsigned int resv21[7]; 315 316 unsigned int i2c1clkctrl; /* offset 0x4A8 */ 317 unsigned int resv22; 318 unsigned int i2c2clkctrl; /* offset 0x4B0 */ 319 unsigned int resv23[3]; 320 unsigned int mmc0clkctrl; /* offset 0x4C0 */ 321 unsigned int resv24; 322 unsigned int mmc1clkctrl; /* offset 0x4C8 */ 323 324 unsigned int resv25[13]; 325 unsigned int spi0clkctrl; /* offset 0x500 */ 326 unsigned int resv26; 327 unsigned int spi1clkctrl; /* offset 0x508 */ 328 unsigned int resv27[9]; 329 unsigned int timer2clkctrl; /* offset 0x530 */ 330 unsigned int resv28; 331 unsigned int timer3clkctrl; /* offset 0x538 */ 332 unsigned int resv29; 333 unsigned int timer4clkctrl; /* offset 0x540 */ 334 unsigned int resv30[5]; 335 unsigned int timer7clkctrl; /* offset 0x558 */ 336 337 unsigned int resv31[9]; 338 unsigned int uart1clkctrl; /* offset 0x580 */ 339 unsigned int resv32; 340 unsigned int uart2clkctrl; /* offset 0x588 */ 341 unsigned int resv33; 342 unsigned int uart3clkctrl; /* offset 0x590 */ 343 unsigned int resv34; 344 unsigned int uart4clkctrl; /* offset 0x598 */ 345 unsigned int resv35; 346 unsigned int uart5clkctrl; /* offset 0x5A0 */ 347 unsigned int resv36[87]; 348 349 unsigned int emifclkstctrl; /* offset 0x700 */ 350 unsigned int resv361[7]; 351 unsigned int emifclkctrl; /* offset 0x720 */ 352 unsigned int resv37[3]; 353 unsigned int emiffwclkctrl; /* offset 0x730 */ 354 unsigned int resv371; 355 unsigned int otfaemifclkctrl; /* offset 0x738 */ 356 unsigned int resv38[57]; 357 unsigned int lcdclkctrl; /* offset 0x820 */ 358 unsigned int resv39[183]; 359 unsigned int cpswclkstctrl; /* offset 0xB00 */ 360 unsigned int resv40[7]; 361 unsigned int cpgmac0clkctrl; /* offset 0xB20 */ 362 }; 363 #endif /* CONFIG_AM43XX */ 364 365 /* Encapsulating Display pll registers */ 366 struct cm_dpll { 367 unsigned int resv1[2]; 368 unsigned int clktimer2clk; /* offset 0x08 */ 369 }; 370 371 /* Control Module RTC registers */ 372 struct cm_rtc { 373 unsigned int rtcclkctrl; /* offset 0x0 */ 374 unsigned int clkstctrl; /* offset 0x4 */ 375 }; 376 377 /* Watchdog timer registers */ 378 struct wd_timer { 379 unsigned int resv1[4]; 380 unsigned int wdtwdsc; /* offset 0x010 */ 381 unsigned int wdtwdst; /* offset 0x014 */ 382 unsigned int wdtwisr; /* offset 0x018 */ 383 unsigned int wdtwier; /* offset 0x01C */ 384 unsigned int wdtwwer; /* offset 0x020 */ 385 unsigned int wdtwclr; /* offset 0x024 */ 386 unsigned int wdtwcrr; /* offset 0x028 */ 387 unsigned int wdtwldr; /* offset 0x02C */ 388 unsigned int wdtwtgr; /* offset 0x030 */ 389 unsigned int wdtwwps; /* offset 0x034 */ 390 unsigned int resv2[3]; 391 unsigned int wdtwdly; /* offset 0x044 */ 392 unsigned int wdtwspr; /* offset 0x048 */ 393 unsigned int resv3[1]; 394 unsigned int wdtwqeoi; /* offset 0x050 */ 395 unsigned int wdtwqstar; /* offset 0x054 */ 396 unsigned int wdtwqsta; /* offset 0x058 */ 397 unsigned int wdtwqens; /* offset 0x05C */ 398 unsigned int wdtwqenc; /* offset 0x060 */ 399 unsigned int resv4[39]; 400 unsigned int wdt_unfr; /* offset 0x100 */ 401 }; 402 403 /* Timer 32 bit registers */ 404 struct gptimer { 405 unsigned int tidr; /* offset 0x00 */ 406 unsigned char res1[12]; 407 unsigned int tiocp_cfg; /* offset 0x10 */ 408 unsigned char res2[12]; 409 unsigned int tier; /* offset 0x20 */ 410 unsigned int tistatr; /* offset 0x24 */ 411 unsigned int tistat; /* offset 0x28 */ 412 unsigned int tisr; /* offset 0x2c */ 413 unsigned int tcicr; /* offset 0x30 */ 414 unsigned int twer; /* offset 0x34 */ 415 unsigned int tclr; /* offset 0x38 */ 416 unsigned int tcrr; /* offset 0x3c */ 417 unsigned int tldr; /* offset 0x40 */ 418 unsigned int ttgr; /* offset 0x44 */ 419 unsigned int twpc; /* offset 0x48 */ 420 unsigned int tmar; /* offset 0x4c */ 421 unsigned int tcar1; /* offset 0x50 */ 422 unsigned int tscir; /* offset 0x54 */ 423 unsigned int tcar2; /* offset 0x58 */ 424 }; 425 426 /* RTC Registers */ 427 struct rtc_regs { 428 unsigned int res[21]; 429 unsigned int osc; /* offset 0x54 */ 430 unsigned int res2[5]; 431 unsigned int kick0r; /* offset 0x6c */ 432 unsigned int kick1r; /* offset 0x70 */ 433 }; 434 435 /* UART Registers */ 436 struct uart_sys { 437 unsigned int resv1[21]; 438 unsigned int uartsyscfg; /* offset 0x54 */ 439 unsigned int uartsyssts; /* offset 0x58 */ 440 }; 441 442 /* VTP Registers */ 443 struct vtp_reg { 444 unsigned int vtp0ctrlreg; 445 }; 446 447 /* Control Status Register */ 448 struct ctrl_stat { 449 unsigned int resv1[16]; 450 unsigned int statusreg; /* ofset 0x40 */ 451 unsigned int resv2[51]; 452 unsigned int secure_emif_sdram_config; /* offset 0x0110 */ 453 }; 454 455 /* AM33XX GPIO registers */ 456 #define OMAP_GPIO_REVISION 0x0000 457 #define OMAP_GPIO_SYSCONFIG 0x0010 458 #define OMAP_GPIO_SYSSTATUS 0x0114 459 #define OMAP_GPIO_IRQSTATUS1 0x002c 460 #define OMAP_GPIO_IRQSTATUS2 0x0030 461 #define OMAP_GPIO_CTRL 0x0130 462 #define OMAP_GPIO_OE 0x0134 463 #define OMAP_GPIO_DATAIN 0x0138 464 #define OMAP_GPIO_DATAOUT 0x013c 465 #define OMAP_GPIO_LEVELDETECT0 0x0140 466 #define OMAP_GPIO_LEVELDETECT1 0x0144 467 #define OMAP_GPIO_RISINGDETECT 0x0148 468 #define OMAP_GPIO_FALLINGDETECT 0x014c 469 #define OMAP_GPIO_DEBOUNCE_EN 0x0150 470 #define OMAP_GPIO_DEBOUNCE_VAL 0x0154 471 #define OMAP_GPIO_CLEARDATAOUT 0x0190 472 #define OMAP_GPIO_SETDATAOUT 0x0194 473 474 /* Control Device Register */ 475 struct ctrl_dev { 476 unsigned int deviceid; /* offset 0x00 */ 477 unsigned int resv1[7]; 478 unsigned int usb_ctrl0; /* offset 0x20 */ 479 unsigned int resv2; 480 unsigned int usb_ctrl1; /* offset 0x28 */ 481 unsigned int resv3; 482 unsigned int macid0l; /* offset 0x30 */ 483 unsigned int macid0h; /* offset 0x34 */ 484 unsigned int macid1l; /* offset 0x38 */ 485 unsigned int macid1h; /* offset 0x3c */ 486 unsigned int resv4[4]; 487 unsigned int miisel; /* offset 0x50 */ 488 }; 489 #endif /* __ASSEMBLY__ */ 490 #endif /* __KERNEL_STRICT_NAMES */ 491 492 #endif /* _AM33XX_CPU_H */ 493