1 /*
2  * clocks_am33xx.h
3  *
4  * AM33xx clock define
5  *
6  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18 
19 #ifndef _CLOCKS_AM33XX_H_
20 #define _CLOCKS_AM33XX_H_
21 
22 #define OSC	(V_OSCK/1000000)
23 
24 /* MAIN PLL Fdll = 550 MHZ, */
25 #define MPUPLL_M	550
26 #define MPUPLL_N	(OSC-1)
27 #define MPUPLL_M2	1
28 
29 /* Core PLL Fdll = 1 GHZ, */
30 #define COREPLL_M	1000
31 #define COREPLL_N	(OSC-1)
32 
33 #define COREPLL_M4	10	/* CORE_CLKOUTM4 = 200 MHZ */
34 #define COREPLL_M5	8	/* CORE_CLKOUTM5 = 250 MHZ */
35 #define COREPLL_M6	4	/* CORE_CLKOUTM6 = 500 MHZ */
36 
37 /*
38  * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
39  * frequency needs to be set to 960 MHZ. Hence,
40  * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
41  */
42 #define PERPLL_M	960
43 #define PERPLL_N	(OSC-1)
44 #define PERPLL_M2	5
45 
46 /* DDR Freq is 266 MHZ for now */
47 /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
48 #define DDRPLL_M	266
49 #define DDRPLL_N	(OSC-1)
50 #define DDRPLL_M2	1
51 
52 extern void pll_init(void);
53 extern void enable_emif_clocks(void);
54 
55 #endif	/* endif _CLOCKS_AM33XX_H_ */
56