1*f87fa62aSChandan Nath /* 2*f87fa62aSChandan Nath * clocks_am33xx.h 3*f87fa62aSChandan Nath * 4*f87fa62aSChandan Nath * AM33xx clock define 5*f87fa62aSChandan Nath * 6*f87fa62aSChandan Nath * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 7*f87fa62aSChandan Nath * 8*f87fa62aSChandan Nath * This program is free software; you can redistribute it and/or 9*f87fa62aSChandan Nath * modify it under the terms of the GNU General Public License as 10*f87fa62aSChandan Nath * published by the Free Software Foundation; either version 2 of 11*f87fa62aSChandan Nath * the License, or (at your option) any later version. 12*f87fa62aSChandan Nath * 13*f87fa62aSChandan Nath * This program is distributed in the hope that it will be useful, 14*f87fa62aSChandan Nath * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*f87fa62aSChandan Nath * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 16*f87fa62aSChandan Nath * GNU General Public License for more details. 17*f87fa62aSChandan Nath */ 18*f87fa62aSChandan Nath 19*f87fa62aSChandan Nath #ifndef _CLOCKS_AM33XX_H_ 20*f87fa62aSChandan Nath #define _CLOCKS_AM33XX_H_ 21*f87fa62aSChandan Nath 22*f87fa62aSChandan Nath #define OSC 24 23*f87fa62aSChandan Nath 24*f87fa62aSChandan Nath /* MAIN PLL Fdll = 550 MHZ, */ 25*f87fa62aSChandan Nath #define MPUPLL_M 550 26*f87fa62aSChandan Nath #define MPUPLL_N 23 27*f87fa62aSChandan Nath #define MPUPLL_M2 1 28*f87fa62aSChandan Nath 29*f87fa62aSChandan Nath /* Core PLL Fdll = 1 GHZ, */ 30*f87fa62aSChandan Nath #define COREPLL_M 1000 31*f87fa62aSChandan Nath #define COREPLL_N 23 32*f87fa62aSChandan Nath 33*f87fa62aSChandan Nath #define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */ 34*f87fa62aSChandan Nath #define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */ 35*f87fa62aSChandan Nath #define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */ 36*f87fa62aSChandan Nath 37*f87fa62aSChandan Nath /* 38*f87fa62aSChandan Nath * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll 39*f87fa62aSChandan Nath * frequency needs to be set to 960 MHZ. Hence, 40*f87fa62aSChandan Nath * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below 41*f87fa62aSChandan Nath */ 42*f87fa62aSChandan Nath #define PERPLL_M 960 43*f87fa62aSChandan Nath #define PERPLL_N 23 44*f87fa62aSChandan Nath #define PERPLL_M2 5 45*f87fa62aSChandan Nath 46*f87fa62aSChandan Nath /* DDR Freq is 266 MHZ for now */ 47*f87fa62aSChandan Nath /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ 48*f87fa62aSChandan Nath #define DDRPLL_M 266 49*f87fa62aSChandan Nath #define DDRPLL_N 23 50*f87fa62aSChandan Nath #define DDRPLL_M2 1 51*f87fa62aSChandan Nath 52*f87fa62aSChandan Nath extern void pll_init(void); 53*f87fa62aSChandan Nath extern void enable_emif_clocks(void); 54*f87fa62aSChandan Nath 55*f87fa62aSChandan Nath #endif /* endif _CLOCKS_AM33XX_H_ */ 56