1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2f87fa62aSChandan Nath /* 3f87fa62aSChandan Nath * clocks_am33xx.h 4f87fa62aSChandan Nath * 5f87fa62aSChandan Nath * AM33xx clock define 6f87fa62aSChandan Nath * 7b43c17cbSMatt Porter * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 8f87fa62aSChandan Nath */ 9f87fa62aSChandan Nath 10f87fa62aSChandan Nath #ifndef _CLOCKS_AM33XX_H_ 11f87fa62aSChandan Nath #define _CLOCKS_AM33XX_H_ 12f87fa62aSChandan Nath 139721027aSTom Rini /* MAIN PLL Fdll supported frequencies */ 149721027aSTom Rini #define MPUPLL_M_1000 1000 159721027aSTom Rini #define MPUPLL_M_800 800 169721027aSTom Rini #define MPUPLL_M_720 720 179721027aSTom Rini #define MPUPLL_M_600 600 1859041a50SLokesh Vutla #define MPUPLL_M_500 500 199721027aSTom Rini #define MPUPLL_M_300 300 209721027aSTom Rini 210660481aSHeiko Schocher #define UART_RESET (0x1 << 1) 220660481aSHeiko Schocher #define UART_CLK_RUNNING_MASK 0x1 230660481aSHeiko Schocher #define UART_SMART_IDLE_EN (0x1 << 0x3) 240660481aSHeiko Schocher 25d3daba10SLokesh Vutla #define CM_DLL_CTRL_NO_OVERRIDE 0x0 26d3daba10SLokesh Vutla #define CM_DLL_READYST 0x4 27d3daba10SLokesh Vutla 28fbd6295dSLokesh Vutla #define NUM_OPPS 6 29fbd6295dSLokesh Vutla 30b43c17cbSMatt Porter extern void enable_dmm_clocks(void); 3186277339STom Rini extern void enable_emif_clocks(void); 3252f7d844SSteve Kipisz extern const struct dpll_params dpll_core_opp100; 3352f7d844SSteve Kipisz extern struct dpll_params dpll_mpu_opp100; 34f87fa62aSChandan Nath 35f87fa62aSChandan Nath #endif /* endif _CLOCKS_AM33XX_H_ */ 36