1f87fa62aSChandan Nath /*
2f87fa62aSChandan Nath  * clocks_am33xx.h
3f87fa62aSChandan Nath  *
4f87fa62aSChandan Nath  * AM33xx clock define
5f87fa62aSChandan Nath  *
6b43c17cbSMatt Porter  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
7f87fa62aSChandan Nath  *
81a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
9f87fa62aSChandan Nath  */
10f87fa62aSChandan Nath 
11f87fa62aSChandan Nath #ifndef _CLOCKS_AM33XX_H_
12f87fa62aSChandan Nath #define _CLOCKS_AM33XX_H_
13f87fa62aSChandan Nath 
149721027aSTom Rini /* MAIN PLL Fdll supported frequencies */
159721027aSTom Rini #define MPUPLL_M_1000	1000
169721027aSTom Rini #define MPUPLL_M_800	800
179721027aSTom Rini #define MPUPLL_M_720	720
189721027aSTom Rini #define MPUPLL_M_600	600
19*59041a50SLokesh Vutla #define MPUPLL_M_500	500
209721027aSTom Rini #define MPUPLL_M_300	300
219721027aSTom Rini 
220660481aSHeiko Schocher #define UART_RESET		(0x1 << 1)
230660481aSHeiko Schocher #define UART_CLK_RUNNING_MASK	0x1
240660481aSHeiko Schocher #define UART_SMART_IDLE_EN	(0x1 << 0x3)
250660481aSHeiko Schocher 
26d3daba10SLokesh Vutla #define CM_DLL_CTRL_NO_OVERRIDE	0x0
27d3daba10SLokesh Vutla #define CM_DLL_READYST		0x4
28d3daba10SLokesh Vutla 
29b43c17cbSMatt Porter extern void enable_dmm_clocks(void);
3052f7d844SSteve Kipisz extern const struct dpll_params dpll_core_opp100;
3152f7d844SSteve Kipisz extern struct dpll_params dpll_mpu_opp100;
32f87fa62aSChandan Nath 
33f87fa62aSChandan Nath #endif	/* endif _CLOCKS_AM33XX_H_ */
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