1f87fa62aSChandan Nath /*
2f87fa62aSChandan Nath  * clocks_am33xx.h
3f87fa62aSChandan Nath  *
4f87fa62aSChandan Nath  * AM33xx clock define
5f87fa62aSChandan Nath  *
6b43c17cbSMatt Porter  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
7f87fa62aSChandan Nath  *
81a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
9f87fa62aSChandan Nath  */
10f87fa62aSChandan Nath 
11f87fa62aSChandan Nath #ifndef _CLOCKS_AM33XX_H_
12f87fa62aSChandan Nath #define _CLOCKS_AM33XX_H_
13f87fa62aSChandan Nath 
14fc33705eSMark Jackson /* MAIN PLL Fdll = 550 MHz, by default */
15fc33705eSMark Jackson #ifndef CONFIG_SYS_MPUCLK
16fc33705eSMark Jackson #define CONFIG_SYS_MPUCLK	550
17fc33705eSMark Jackson #endif
18f87fa62aSChandan Nath 
19*0660481aSHeiko Schocher #define UART_RESET		(0x1 << 1)
20*0660481aSHeiko Schocher #define UART_CLK_RUNNING_MASK	0x1
21*0660481aSHeiko Schocher #define UART_SMART_IDLE_EN	(0x1 << 0x3)
22*0660481aSHeiko Schocher 
23b43c17cbSMatt Porter extern void enable_dmm_clocks(void);
24f87fa62aSChandan Nath 
25f87fa62aSChandan Nath #endif	/* endif _CLOCKS_AM33XX_H_ */
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