1 /*
2  * clock.h
3  *
4  * clock header
5  *
6  * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #ifndef _CLOCKS_H_
12 #define _CLOCKS_H_
13 
14 #include <asm/arch/clocks_am33xx.h>
15 
16 #ifdef CONFIG_TI81XX
17 #include <asm/arch/clock_ti81xx.h>
18 #endif
19 
20 #define LDELAY 1000000
21 
22 /*CM_<clock_domain>__CLKCTRL */
23 #define CD_CLKCTRL_CLKTRCTRL_SHIFT		0
24 #define CD_CLKCTRL_CLKTRCTRL_MASK		3
25 
26 #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP		0
27 #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP		1
28 #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP		2
29 
30 /* CM_<clock_domain>_<module>_CLKCTRL */
31 #define MODULE_CLKCTRL_MODULEMODE_SHIFT		0
32 #define MODULE_CLKCTRL_MODULEMODE_MASK		3
33 #define MODULE_CLKCTRL_IDLEST_SHIFT		16
34 #define MODULE_CLKCTRL_IDLEST_MASK		(3 << 16)
35 
36 #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE		0
37 #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN	2
38 
39 #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL	0
40 #define MODULE_CLKCTRL_IDLEST_TRANSITIONING	1
41 #define MODULE_CLKCTRL_IDLEST_IDLE		2
42 #define MODULE_CLKCTRL_IDLEST_DISABLED		3
43 
44 /* CM_CLKMODE_DPLL */
45 #define CM_CLKMODE_DPLL_SSC_EN_SHIFT		12
46 #define CM_CLKMODE_DPLL_SSC_EN_MASK		(1 << 12)
47 #define CM_CLKMODE_DPLL_SSC_ACK_MASK		(1 << 13)
48 #define CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK	(1 << 14)
49 #define CM_CLKMODE_DPLL_SSC_TYPE_MASK		(1 << 15)
50 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
51 #define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
52 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
53 #define CM_CLKMODE_DPLL_LPMODE_EN_MASK		(1 << 10)
54 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT	9
55 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK	(1 << 9)
56 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT	8
57 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK	(1 << 8)
58 #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT		5
59 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK		(0x7 << 5)
60 #define CM_CLKMODE_DPLL_EN_SHIFT		0
61 #define CM_CLKMODE_DPLL_EN_MASK			(0x7 << 0)
62 
63 #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
64 #define CM_CLKMODE_DPLL_DPLL_EN_MASK		7
65 
66 #define DPLL_EN_STOP			1
67 #define DPLL_EN_MN_BYPASS		4
68 #define DPLL_EN_LOW_POWER_BYPASS	5
69 #define DPLL_EN_LOCK			7
70 
71 /* CM_IDLEST_DPLL fields */
72 #define ST_DPLL_CLK_MASK		1
73 
74 /* CM_CLKSEL_DPLL */
75 #define CM_CLKSEL_DPLL_M_SHIFT			8
76 #define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
77 #define CM_CLKSEL_DPLL_N_SHIFT			0
78 #define CM_CLKSEL_DPLL_N_MASK			0x7F
79 
80 struct dpll_params {
81 	u32 m;
82 	u32 n;
83 	s8 m2;
84 	s8 m3;
85 	s8 m4;
86 	s8 m5;
87 	s8 m6;
88 };
89 
90 struct dpll_regs {
91 	u32 cm_clkmode_dpll;
92 	u32 cm_idlest_dpll;
93 	u32 cm_autoidle_dpll;
94 	u32 cm_clksel_dpll;
95 	u32 cm_div_m2_dpll;
96 	u32 cm_div_m3_dpll;
97 	u32 cm_div_m4_dpll;
98 	u32 cm_div_m5_dpll;
99 	u32 cm_div_m6_dpll;
100 };
101 
102 extern const struct dpll_regs dpll_mpu_regs;
103 extern const struct dpll_regs dpll_core_regs;
104 extern const struct dpll_regs dpll_per_regs;
105 extern const struct dpll_regs dpll_ddr_regs;
106 
107 extern struct cm_wkuppll *const cmwkup;
108 
109 const struct dpll_params *get_dpll_mpu_params(void);
110 const struct dpll_params *get_dpll_core_params(void);
111 const struct dpll_params *get_dpll_per_params(void);
112 const struct dpll_params *get_dpll_ddr_params(void);
113 void scale_vcores(void);
114 void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
115 void prcm_init(void);
116 void enable_basic_clocks(void);
117 void do_enable_clocks(u32 *const *, u32 *const *, u8);
118 void do_disable_clocks(u32 *const *, u32 *const *, u8);
119 
120 void set_mpu_spreadspectrum(int permille);
121 #endif
122