1 /* 2 * clock.h 3 * 4 * clock header 5 * 6 * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _CLOCKS_H_ 12 #define _CLOCKS_H_ 13 14 #include <asm/arch/clocks_am33xx.h> 15 16 #ifdef CONFIG_TI81XX 17 #include <asm/arch/clock_ti81xx.h> 18 #endif 19 20 #define LDELAY 1000000 21 22 /*CM_<clock_domain>__CLKCTRL */ 23 #define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 24 #define CD_CLKCTRL_CLKTRCTRL_MASK 3 25 26 #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 27 #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 28 #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 29 30 /* CM_<clock_domain>_<module>_CLKCTRL */ 31 #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 32 #define MODULE_CLKCTRL_MODULEMODE_MASK 3 33 #define MODULE_CLKCTRL_IDLEST_SHIFT 16 34 #define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) 35 36 #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 37 #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 38 39 #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 40 #define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 41 #define MODULE_CLKCTRL_IDLEST_IDLE 2 42 #define MODULE_CLKCTRL_IDLEST_DISABLED 3 43 44 /* CM_CLKMODE_DPLL */ 45 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 46 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) 47 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 48 #define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) 49 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 50 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) 51 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 52 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 53 #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 54 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) 55 #define CM_CLKMODE_DPLL_EN_SHIFT 0 56 #define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) 57 58 #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 59 #define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 60 61 #define DPLL_EN_STOP 1 62 #define DPLL_EN_MN_BYPASS 4 63 #define DPLL_EN_LOW_POWER_BYPASS 5 64 #define DPLL_EN_LOCK 7 65 66 /* CM_IDLEST_DPLL fields */ 67 #define ST_DPLL_CLK_MASK 1 68 69 /* CM_CLKSEL_DPLL */ 70 #define CM_CLKSEL_DPLL_M_SHIFT 8 71 #define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) 72 #define CM_CLKSEL_DPLL_N_SHIFT 0 73 #define CM_CLKSEL_DPLL_N_MASK 0x7F 74 75 struct dpll_params { 76 u32 m; 77 u32 n; 78 s8 m2; 79 s8 m3; 80 s8 m4; 81 s8 m5; 82 s8 m6; 83 }; 84 85 struct dpll_regs { 86 u32 cm_clkmode_dpll; 87 u32 cm_idlest_dpll; 88 u32 cm_autoidle_dpll; 89 u32 cm_clksel_dpll; 90 u32 cm_div_m2_dpll; 91 u32 cm_div_m3_dpll; 92 u32 cm_div_m4_dpll; 93 u32 cm_div_m5_dpll; 94 u32 cm_div_m6_dpll; 95 }; 96 97 extern const struct dpll_regs dpll_mpu_regs; 98 extern const struct dpll_regs dpll_core_regs; 99 extern const struct dpll_regs dpll_per_regs; 100 extern const struct dpll_regs dpll_ddr_regs; 101 102 extern struct cm_wkuppll *const cmwkup; 103 104 const struct dpll_params *get_dpll_mpu_params(void); 105 const struct dpll_params *get_dpll_core_params(void); 106 const struct dpll_params *get_dpll_per_params(void); 107 const struct dpll_params *get_dpll_ddr_params(void); 108 void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); 109 void prcm_init(void); 110 void enable_basic_clocks(void); 111 void do_enable_clocks(u32 *const *, u32 *const *, u8); 112 113 #endif 114