1 /* 2 * clock.h 3 * 4 * clock header 5 * 6 * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _CLOCKS_H_ 12 #define _CLOCKS_H_ 13 14 #include <asm/arch/clocks_am33xx.h> 15 16 #define LDELAY 1000000 17 18 /*CM_<clock_domain>__CLKCTRL */ 19 #define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 20 #define CD_CLKCTRL_CLKTRCTRL_MASK 3 21 22 #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 23 #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 24 #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 25 26 /* CM_<clock_domain>_<module>_CLKCTRL */ 27 #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 28 #define MODULE_CLKCTRL_MODULEMODE_MASK 3 29 #define MODULE_CLKCTRL_IDLEST_SHIFT 16 30 #define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) 31 32 #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 33 #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 34 35 #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 36 #define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 37 #define MODULE_CLKCTRL_IDLEST_IDLE 2 38 #define MODULE_CLKCTRL_IDLEST_DISABLED 3 39 40 /* CM_CLKMODE_DPLL */ 41 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 42 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) 43 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 44 #define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) 45 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 46 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) 47 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 48 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 49 #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 50 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) 51 #define CM_CLKMODE_DPLL_EN_SHIFT 0 52 #define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) 53 54 #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 55 #define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 56 57 #define DPLL_EN_STOP 1 58 #define DPLL_EN_MN_BYPASS 4 59 #define DPLL_EN_LOW_POWER_BYPASS 5 60 #define DPLL_EN_LOCK 7 61 62 /* CM_IDLEST_DPLL fields */ 63 #define ST_DPLL_CLK_MASK 1 64 65 /* CM_CLKSEL_DPLL */ 66 #define CM_CLKSEL_DPLL_M_SHIFT 8 67 #define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) 68 #define CM_CLKSEL_DPLL_N_SHIFT 0 69 #define CM_CLKSEL_DPLL_N_MASK 0x7F 70 71 struct dpll_params { 72 u32 m; 73 u32 n; 74 s8 m2; 75 s8 m3; 76 s8 m4; 77 s8 m5; 78 s8 m6; 79 }; 80 81 struct dpll_regs { 82 u32 cm_clkmode_dpll; 83 u32 cm_idlest_dpll; 84 u32 cm_autoidle_dpll; 85 u32 cm_clksel_dpll; 86 u32 cm_div_m2_dpll; 87 u32 cm_div_m3_dpll; 88 u32 cm_div_m4_dpll; 89 u32 cm_div_m5_dpll; 90 u32 cm_div_m6_dpll; 91 }; 92 93 extern const struct dpll_regs dpll_mpu_regs; 94 extern const struct dpll_regs dpll_core_regs; 95 extern const struct dpll_regs dpll_per_regs; 96 extern const struct dpll_regs dpll_ddr_regs; 97 extern const struct dpll_params dpll_mpu; 98 extern const struct dpll_params dpll_core; 99 extern const struct dpll_params dpll_per; 100 extern const struct dpll_params dpll_ddr; 101 102 extern struct cm_wkuppll *const cmwkup; 103 104 const struct dpll_params *get_dpll_ddr_params(void); 105 void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); 106 void prcm_init(void); 107 void enable_basic_clocks(void); 108 void do_enable_clocks(u32 *const *, u32 *const *, u8); 109 110 #endif 111