1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 23164f3c6SLokesh Vutla /* 33164f3c6SLokesh Vutla * clk-synthesizer.h 43164f3c6SLokesh Vutla * 53164f3c6SLokesh Vutla * Clock synthesizer header 63164f3c6SLokesh Vutla * 73164f3c6SLokesh Vutla * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/ 83164f3c6SLokesh Vutla */ 93164f3c6SLokesh Vutla 103164f3c6SLokesh Vutla #ifndef __CLK_SYNTHESIZER_H 113164f3c6SLokesh Vutla #define __CLK_SYNTHESIZER_H 123164f3c6SLokesh Vutla 133164f3c6SLokesh Vutla #include <common.h> 143164f3c6SLokesh Vutla 153164f3c6SLokesh Vutla #define CLK_SYNTHESIZER_ID_REG 0x0 163164f3c6SLokesh Vutla #define CLK_SYNTHESIZER_XCSEL 0x05 173164f3c6SLokesh Vutla #define CLK_SYNTHESIZER_MUX_REG 0x14 183164f3c6SLokesh Vutla #define CLK_SYNTHESIZER_PDIV2_REG 0x16 193164f3c6SLokesh Vutla #define CLK_SYNTHESIZER_PDIV3_REG 0x17 203164f3c6SLokesh Vutla 213164f3c6SLokesh Vutla #define CLK_SYNTHESIZER_BYTE_MODE 0x80 223164f3c6SLokesh Vutla 233164f3c6SLokesh Vutla /** 243164f3c6SLokesh Vutla * struct clk_synth: This structure holds data neeed for configuring 253164f3c6SLokesh Vutla * for clock synthesizer. 263164f3c6SLokesh Vutla * @id: The id of synthesizer 273164f3c6SLokesh Vutla * @capacitor: value of the capacitor attached 283164f3c6SLokesh Vutla * @mux: mux settings. 293164f3c6SLokesh Vutla * @pdiv2: Div to be applied to second output 303164f3c6SLokesh Vutla * @pdiv3: Div to be applied to third output 313164f3c6SLokesh Vutla */ 323164f3c6SLokesh Vutla struct clk_synth { 333164f3c6SLokesh Vutla u32 id; 343164f3c6SLokesh Vutla u32 capacitor; 353164f3c6SLokesh Vutla u32 mux; 363164f3c6SLokesh Vutla u32 pdiv2; 373164f3c6SLokesh Vutla u32 pdiv3; 383164f3c6SLokesh Vutla }; 393164f3c6SLokesh Vutla 403164f3c6SLokesh Vutla int setup_clock_synthesizer(struct clk_synth *data); 413164f3c6SLokesh Vutla 423164f3c6SLokesh Vutla #endif 43