1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU111
4 *
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/phy/phy.h>
17
18/ {
19	model = "ZynqMP ZCU111 RevA";
20	compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
21
22	aliases {
23		ethernet0 = &gem3;
24		gpio0 = &gpio;
25		i2c0 = &i2c0;
26		i2c1 = &i2c1;
27		mmc0 = &sdhci1;
28		rtc0 = &rtc;
29		serial0 = &uart0;
30		serial1 = &dcc;
31		spi0 = &qspi;
32		usb0 = &usb0;
33	};
34
35	chosen {
36		bootargs = "earlycon";
37		stdout-path = "serial0:115200n8";
38		xlnx,eeprom = &eeprom;
39	};
40
41	memory@0 {
42		device_type = "memory";
43		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
44		/* Another 4GB connected to PL */
45	};
46
47	gpio-keys {
48		compatible = "gpio-keys";
49		autorepeat;
50		sw19 {
51			label = "sw19";
52			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
53			linux,code = <KEY_DOWN>;
54			gpio-key,wakeup;
55			autorepeat;
56		};
57	};
58
59	leds {
60		compatible = "gpio-leds";
61		heartbeat_led {
62			label = "heartbeat";
63			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
64			linux,default-trigger = "heartbeat";
65		};
66	};
67};
68
69&dcc {
70	status = "okay";
71};
72
73&fpd_dma_chan1 {
74	status = "okay";
75};
76
77&fpd_dma_chan2 {
78	status = "okay";
79};
80
81&fpd_dma_chan3 {
82	status = "okay";
83};
84
85&fpd_dma_chan4 {
86	status = "okay";
87};
88
89&fpd_dma_chan5 {
90	status = "okay";
91};
92
93&fpd_dma_chan6 {
94	status = "okay";
95};
96
97&fpd_dma_chan7 {
98	status = "okay";
99};
100
101&fpd_dma_chan8 {
102	status = "okay";
103};
104
105&gem3 {
106	status = "okay";
107	phy-handle = <&phy0>;
108	phy-mode = "rgmii-id";
109	phy0: phy@c {
110		reg = <0xc>;
111		ti,rx-internal-delay = <0x8>;
112		ti,tx-internal-delay = <0xa>;
113		ti,fifo-depth = <0x1>;
114	};
115};
116
117&gpio {
118	status = "okay";
119};
120
121&gpu {
122	status = "okay";
123};
124
125&i2c0 {
126	status = "okay";
127	clock-frequency = <400000>;
128
129	tca6416_u22: gpio@20 {
130		compatible = "ti,tca6416";
131		reg = <0x20>;
132		gpio-controller; /* interrupt not connected */
133		#gpio-cells = <2>;
134		/*
135		 * IRQ not connected
136		 * Lines:
137		 * 0 - MAX6643_OT_B
138		 * 1 - MAX6643_FANFAIL_B
139		 * 2 - MIO26_PMU_INPUT_LS
140		 * 4 - SFP_SI5382_INT_ALM
141		 * 5 - IIC_MUX_RESET_B
142		 * 6 - GEM3_EXP_RESET_B
143		 * 10 - FMCP_HSPC_PRSNT_M2C_B
144		 * 11 - CLK_SPI_MUX_SEL0
145		 * 12 - CLK_SPI_MUX_SEL1
146		 * 16 - IRPS5401_ALERT_B
147		 * 17 - INA226_PMBUS_ALERT
148		 * 3, 7, 13-15 - not connected
149		 */
150	};
151
152	i2c-mux@75 { /* u23 */
153		compatible = "nxp,pca9544";
154		#address-cells = <1>;
155		#size-cells = <0>;
156		reg = <0x75>;
157		i2c@0 {
158			#address-cells = <1>;
159			#size-cells = <0>;
160			reg = <0>;
161			/* PS_PMBUS */
162			/* PMBUS_ALERT done via pca9544 */
163			ina226@40 { /* u67 */
164				compatible = "ti,ina226";
165				reg = <0x40>;
166				shunt-resistor = <2000>;
167			};
168			ina226@41 { /* u59 */
169				compatible = "ti,ina226";
170				reg = <0x41>;
171				shunt-resistor = <5000>;
172			};
173			ina226@42 { /* u61 */
174				compatible = "ti,ina226";
175				reg = <0x42>;
176				shunt-resistor = <5000>;
177			};
178			ina226@43 { /* u60 */
179				compatible = "ti,ina226";
180				reg = <0x43>;
181				shunt-resistor = <5000>;
182			};
183			ina226@45 { /* u64 */
184				compatible = "ti,ina226";
185				reg = <0x45>;
186				shunt-resistor = <5000>;
187			};
188			ina226@46 { /* u69 */
189				compatible = "ti,ina226";
190				reg = <0x46>;
191				shunt-resistor = <2000>;
192			};
193			ina226@47 { /* u66 */
194				compatible = "ti,ina226";
195				reg = <0x47>;
196				shunt-resistor = <5000>;
197			};
198			ina226@48 { /* u65 */
199				compatible = "ti,ina226";
200				reg = <0x48>;
201				shunt-resistor = <5000>;
202			};
203			ina226@49 { /* u63 */
204				compatible = "ti,ina226";
205				reg = <0x49>;
206				shunt-resistor = <5000>;
207			};
208			ina226@4a { /* u3 */
209				compatible = "ti,ina226";
210				reg = <0x4a>;
211				shunt-resistor = <5000>;
212			};
213			ina226@4b { /* u71 */
214				compatible = "ti,ina226";
215				reg = <0x4b>;
216				shunt-resistor = <5000>;
217			};
218			ina226@4c { /* u77 */
219				compatible = "ti,ina226";
220				reg = <0x4c>;
221				shunt-resistor = <5000>;
222			};
223			ina226@4d { /* u73 */
224				compatible = "ti,ina226";
225				reg = <0x4d>;
226				shunt-resistor = <5000>;
227			};
228			ina226@4e { /* u79 */
229				compatible = "ti,ina226";
230				reg = <0x4e>;
231				shunt-resistor = <5000>;
232			};
233		};
234		i2c@1 {
235			#address-cells = <1>;
236			#size-cells = <0>;
237			reg = <1>;
238			/* NC */
239		};
240		i2c@2 {
241			#address-cells = <1>;
242			#size-cells = <0>;
243			reg = <2>;
244			irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
245				#clock-cells = <0>;
246				compatible = "infineon,irps5401";
247				reg = <0x43>;
248			};
249			irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
250				#clock-cells = <0>;
251				compatible = "infineon,irps5401";
252				reg = <0x44>;
253			};
254			irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
255				#clock-cells = <0>;
256				compatible = "infineon,irps5401";
257				reg = <0x45>;
258			};
259			/* u68 IR38064 +0 */
260			/* u70 IR38060 +1 */
261			/* u74 IR38060 +2 */
262			/* u75 IR38060 +6 */
263			/* J19 header too */
264
265		};
266		i2c@3 {
267			#address-cells = <1>;
268			#size-cells = <0>;
269			reg = <3>;
270			/* SYSMON */
271		};
272	};
273};
274
275&i2c1 {
276	status = "okay";
277	clock-frequency = <400000>;
278
279	i2c-mux@74 { /* u26 */
280		compatible = "nxp,pca9548";
281		#address-cells = <1>;
282		#size-cells = <0>;
283		reg = <0x74>;
284		i2c@0 {
285			#address-cells = <1>;
286			#size-cells = <0>;
287			reg = <0>;
288			/*
289			 * IIC_EEPROM 1kB memory which uses 256B blocks
290			 * where every block has different address.
291			 *    0 - 256B address 0x54
292			 * 256B - 512B address 0x55
293			 * 512B - 768B address 0x56
294			 * 768B - 1024B address 0x57
295			 */
296			eeprom: eeprom@54 { /* u88 */
297				compatible = "atmel,24c08";
298				reg = <0x54>;
299			};
300		};
301		i2c@1 {
302			#address-cells = <1>;
303			#size-cells = <0>;
304			reg = <1>;
305			si5341: clock-generator@36 { /* SI5341 - u46 */
306				compatible = "si5341";
307				reg = <0x36>;
308			};
309
310		};
311		i2c@2 {
312			#address-cells = <1>;
313			#size-cells = <0>;
314			reg = <2>;
315			si570_1: clock-generator@5d { /* USER SI570 - u47 */
316				#clock-cells = <0>;
317				compatible = "silabs,si570";
318				reg = <0x5d>;
319				temperature-stability = <50>;
320				factory-fout = <300000000>;
321				clock-frequency = <300000000>;
322				clock-output-names = "si570_user";
323			};
324		};
325		i2c@3 {
326			#address-cells = <1>;
327			#size-cells = <0>;
328			reg = <3>;
329			si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
330				#clock-cells = <0>;
331				compatible = "silabs,si570";
332				reg = <0x5d>;
333				temperature-stability = <50>;
334				factory-fout = <156250000>;
335				clock-frequency = <148500000>;
336				clock-output-names = "si570_mgt";
337			};
338		};
339		i2c@4 {
340			#address-cells = <1>;
341			#size-cells = <0>;
342			reg = <4>;
343			si5328: clock-generator@69 { /* SI5328 - u48 */
344				compatible = "silabs,si5328";
345				reg = <0x69>;
346			};
347		};
348		i2c@5 {
349			#address-cells = <1>;
350			#size-cells = <0>;
351			reg = <5>;
352				sc18is603@2f { /* sc18is602 - u93 */
353					compatible = "nxp,sc18is603";
354					reg = <0x2f>;
355					/* 4 gpios for CS not handled by driver */
356					/*
357					 * USB2ANY cable or
358					 * LMK04208 - u90 or
359					 * LMX2594 - u102 or
360					 * LMX2594 - u103 or
361					 * LMX2594 - u104
362					 */
363				};
364		};
365		i2c@6 {
366			#address-cells = <1>;
367			#size-cells = <0>;
368			reg = <6>;
369			/* FMC connector */
370		};
371		/* 7 NC */
372	};
373
374	i2c-mux@75 {
375		compatible = "nxp,pca9548"; /* u27 */
376		#address-cells = <1>;
377		#size-cells = <0>;
378		reg = <0x75>;
379
380		i2c@0 {
381			#address-cells = <1>;
382			#size-cells = <0>;
383			reg = <0>;
384			/* FMCP_HSPC_IIC */
385		};
386		i2c@1 {
387			#address-cells = <1>;
388			#size-cells = <0>;
389			reg = <1>;
390			/* NC */
391		};
392		i2c@2 {
393			#address-cells = <1>;
394			#size-cells = <0>;
395			reg = <2>;
396			/* SYSMON */
397		};
398		i2c@3 {
399			#address-cells = <1>;
400			#size-cells = <0>;
401			reg = <3>;
402			/* DDR4 SODIMM */
403		};
404		i2c@4 {
405			#address-cells = <1>;
406			#size-cells = <0>;
407			reg = <4>;
408			/* SFP3 */
409		};
410		i2c@5 {
411			#address-cells = <1>;
412			#size-cells = <0>;
413			reg = <5>;
414			/* SFP2 */
415		};
416		i2c@6 {
417			#address-cells = <1>;
418			#size-cells = <0>;
419			reg = <6>;
420			/* SFP1 */
421		};
422		i2c@7 {
423			#address-cells = <1>;
424			#size-cells = <0>;
425			reg = <7>;
426			/* SFP0 */
427		};
428	};
429};
430
431&qspi {
432	status = "okay";
433	is-dual = <1>;
434	flash@0 {
435		compatible = "m25p80", "spi-flash"; /* 32MB */
436		#address-cells = <1>;
437		#size-cells = <1>;
438		reg = <0x0>;
439		spi-tx-bus-width = <1>;
440		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
441		spi-max-frequency = <108000000>; /* Based on DC1 spec */
442		partition@qspi-fsbl-uboot { /* for testing purpose */
443			label = "qspi-fsbl-uboot";
444			reg = <0x0 0x100000>;
445		};
446		partition@qspi-linux { /* for testing purpose */
447			label = "qspi-linux";
448			reg = <0x100000 0x500000>;
449		};
450		partition@qspi-device-tree { /* for testing purpose */
451			label = "qspi-device-tree";
452			reg = <0x600000 0x20000>;
453		};
454		partition@qspi-rootfs { /* for testing purpose */
455			label = "qspi-rootfs";
456			reg = <0x620000 0x5E0000>;
457		};
458	};
459};
460
461&rtc {
462	status = "okay";
463};
464
465&sata {
466	status = "okay";
467	/* SATA OOB timing settings */
468	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
469	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
470	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
471	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
472	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
473	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
474	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
475	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
476	phy-names = "sata-phy";
477	phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
478};
479
480/* SD1 with level shifter */
481&sdhci1 {
482	status = "okay";
483	no-1-8-v;
484	disable-wp;
485	xlnx,mio_bank = <1>;
486};
487
488&serdes {
489	status = "okay";
490};
491
492&uart0 {
493	status = "okay";
494};
495
496/* ULPI SMSC USB3320 */
497&usb0 {
498	status = "okay";
499};
500
501&dwc3_0 {
502	status = "okay";
503	dr_mode = "host";
504	snps,usb3_lpm_capable;
505	phy-names = "usb3-phy";
506	phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
507};
508