1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU106
4 *
5 * (C) Copyright 2016, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/phy/phy.h>
17
18/ {
19	model = "ZynqMP ZCU106 RevA";
20	compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
21
22	aliases {
23		ethernet0 = &gem3;
24		gpio0 = &gpio;
25		i2c0 = &i2c0;
26		i2c1 = &i2c1;
27		mmc0 = &sdhci1;
28		rtc0 = &rtc;
29		serial0 = &uart0;
30		serial1 = &uart1;
31		serial2 = &dcc;
32		spi0 = &qspi;
33		usb0 = &usb0;
34	};
35
36	chosen {
37		bootargs = "earlycon";
38		stdout-path = "serial0:115200n8";
39		xlnx,eeprom = &eeprom;
40	};
41
42	memory@0 {
43		device_type = "memory";
44		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
45	};
46
47	gpio-keys {
48		compatible = "gpio-keys";
49		autorepeat;
50		sw19 {
51			label = "sw19";
52			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
53			linux,code = <KEY_DOWN>;
54			gpio-key,wakeup;
55			autorepeat;
56		};
57	};
58
59	leds {
60		compatible = "gpio-leds";
61		heartbeat_led {
62			label = "heartbeat";
63			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
64			linux,default-trigger = "heartbeat";
65		};
66	};
67};
68
69&can1 {
70	status = "okay";
71};
72
73&dcc {
74	status = "okay";
75};
76
77&fpd_dma_chan1 {
78	status = "okay";
79};
80
81&fpd_dma_chan2 {
82	status = "okay";
83};
84
85&fpd_dma_chan3 {
86	status = "okay";
87};
88
89&fpd_dma_chan4 {
90	status = "okay";
91};
92
93&fpd_dma_chan5 {
94	status = "okay";
95};
96
97&fpd_dma_chan6 {
98	status = "okay";
99};
100
101&fpd_dma_chan7 {
102	status = "okay";
103};
104
105&fpd_dma_chan8 {
106	status = "okay";
107};
108
109&gem3 {
110	status = "okay";
111	phy-handle = <&phy0>;
112	phy-mode = "rgmii-id";
113	phy0: phy@c {
114		reg = <0xc>;
115		ti,rx-internal-delay = <0x8>;
116		ti,tx-internal-delay = <0xa>;
117		ti,fifo-depth = <0x1>;
118	};
119};
120
121&gpio {
122	status = "okay";
123};
124
125&gpu {
126	status = "okay";
127};
128
129&i2c0 {
130	status = "okay";
131	clock-frequency = <400000>;
132
133	tca6416_u97: gpio@20 {
134		compatible = "ti,tca6416";
135		reg = <0x20>;
136		gpio-controller; /* interrupt not connected */
137		#gpio-cells = <2>;
138		/*
139		 * IRQ not connected
140		 * Lines:
141		 * 0 - SFP_SI5328_INT_ALM
142		 * 1 - HDMI_SI5328_INT_ALM
143		 * 5 - IIC_MUX_RESET_B
144		 * 6 - GEM3_EXP_RESET_B
145		 * 10 - FMC_HPC0_PRSNT_M2C_B
146		 * 11 - FMC_HPC1_PRSNT_M2C_B
147		 * 2-4, 7, 12-17 - not connected
148		 */
149	};
150
151	tca6416_u61: gpio@21 {
152		compatible = "ti,tca6416";
153		reg = <0x21>;
154		gpio-controller;
155		#gpio-cells = <2>;
156		/*
157		 * IRQ not connected
158		 * Lines:
159		 * 0 - VCCPSPLL_EN
160		 * 1 - MGTRAVCC_EN
161		 * 2 - MGTRAVTT_EN
162		 * 3 - VCCPSDDRPLL_EN
163		 * 4 - MIO26_PMU_INPUT_LS
164		 * 5 - PL_PMBUS_ALERT
165		 * 6 - PS_PMBUS_ALERT
166		 * 7 - MAXIM_PMBUS_ALERT
167		 * 10 - PL_DDR4_VTERM_EN
168		 * 11 - PL_DDR4_VPP_2V5_EN
169		 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
170		 * 13 - PS_DIMM_SUSPEND_EN
171		 * 14 - PS_DDR4_VTERM_EN
172		 * 15 - PS_DDR4_VPP_2V5_EN
173		 * 16 - 17 - not connected
174		 */
175	};
176
177	i2c-mux@75 { /* u60 */
178		compatible = "nxp,pca9544";
179		#address-cells = <1>;
180		#size-cells = <0>;
181		reg = <0x75>;
182		i2c@0 {
183			#address-cells = <1>;
184			#size-cells = <0>;
185			reg = <0>;
186			/* PS_PMBUS */
187			ina226@40 { /* u76 */
188				compatible = "ti,ina226";
189				reg = <0x40>;
190				shunt-resistor = <5000>;
191			};
192			ina226@41 { /* u77 */
193				compatible = "ti,ina226";
194				reg = <0x41>;
195				shunt-resistor = <5000>;
196			};
197			ina226@42 { /* u78 */
198				compatible = "ti,ina226";
199				reg = <0x42>;
200				shunt-resistor = <5000>;
201			};
202			ina226@43 { /* u87 */
203				compatible = "ti,ina226";
204				reg = <0x43>;
205				shunt-resistor = <5000>;
206			};
207			ina226@44 { /* u85 */
208				compatible = "ti,ina226";
209				reg = <0x44>;
210				shunt-resistor = <5000>;
211			};
212			ina226@45 { /* u86 */
213				compatible = "ti,ina226";
214				reg = <0x45>;
215				shunt-resistor = <5000>;
216			};
217			ina226@46 { /* u93 */
218				compatible = "ti,ina226";
219				reg = <0x46>;
220				shunt-resistor = <5000>;
221			};
222			ina226@47 { /* u88 */
223				compatible = "ti,ina226";
224				reg = <0x47>;
225				shunt-resistor = <5000>;
226			};
227			ina226@4a { /* u15 */
228				compatible = "ti,ina226";
229				reg = <0x4a>;
230				shunt-resistor = <5000>;
231			};
232			ina226@4b { /* u92 */
233				compatible = "ti,ina226";
234				reg = <0x4b>;
235				shunt-resistor = <5000>;
236			};
237		};
238		i2c@1 {
239			#address-cells = <1>;
240			#size-cells = <0>;
241			reg = <1>;
242			/* PL_PMBUS */
243			ina226@40 { /* u79 */
244				compatible = "ti,ina226";
245				reg = <0x40>;
246				shunt-resistor = <2000>;
247			};
248			ina226@41 { /* u81 */
249				compatible = "ti,ina226";
250				reg = <0x41>;
251				shunt-resistor = <5000>;
252			};
253			ina226@42 { /* u80 */
254				compatible = "ti,ina226";
255				reg = <0x42>;
256				shunt-resistor = <5000>;
257			};
258			ina226@43 { /* u84 */
259				compatible = "ti,ina226";
260				reg = <0x43>;
261				shunt-resistor = <5000>;
262			};
263			ina226@44 { /* u16 */
264				compatible = "ti,ina226";
265				reg = <0x44>;
266				shunt-resistor = <5000>;
267			};
268			ina226@45 { /* u65 */
269				compatible = "ti,ina226";
270				reg = <0x45>;
271				shunt-resistor = <5000>;
272			};
273			ina226@46 { /* u74 */
274				compatible = "ti,ina226";
275				reg = <0x46>;
276				shunt-resistor = <5000>;
277			};
278			ina226@47 { /* u75 */
279				compatible = "ti,ina226";
280				reg = <0x47>;
281				shunt-resistor = <5000>;
282			};
283		};
284		i2c@2 {
285			#address-cells = <1>;
286			#size-cells = <0>;
287			reg = <2>;
288			/* MAXIM_PMBUS - 00 */
289			max15301@a { /* u46 */
290				compatible = "maxim,max15301";
291				reg = <0xa>;
292			};
293			max15303@b { /* u4 */
294				compatible = "maxim,max15303";
295				reg = <0xb>;
296			};
297			max15303@10 { /* u13 */
298				compatible = "maxim,max15303";
299				reg = <0x10>;
300			};
301			max15301@13 { /* u47 */
302				compatible = "maxim,max15301";
303				reg = <0x13>;
304			};
305			max15303@14 { /* u7 */
306				compatible = "maxim,max15303";
307				reg = <0x14>;
308			};
309			max15303@15 { /* u6 */
310				compatible = "maxim,max15303";
311				reg = <0x15>;
312			};
313			max15303@16 { /* u10 */
314				compatible = "maxim,max15303";
315				reg = <0x16>;
316			};
317			max15303@17 { /* u9 */
318				compatible = "maxim,max15303";
319				reg = <0x17>;
320			};
321			max15301@18 { /* u63 */
322				compatible = "maxim,max15301";
323				reg = <0x18>;
324			};
325			max15303@1a { /* u49 */
326				compatible = "maxim,max15303";
327				reg = <0x1a>;
328			};
329			max15303@1b { /* u8 */
330				compatible = "maxim,max15303";
331				reg = <0x1b>;
332			};
333			max15303@1d { /* u18 */
334				compatible = "maxim,max15303";
335				reg = <0x1d>;
336			};
337
338			max20751@72 { /* u95 */
339				compatible = "maxim,max20751";
340				reg = <0x72>;
341			};
342			max20751@73 { /* u96 */
343				compatible = "maxim,max20751";
344				reg = <0x73>;
345			};
346		};
347		/* Bus 3 is not connected */
348	};
349};
350
351&i2c1 {
352	status = "okay";
353	clock-frequency = <400000>;
354
355	/* PL i2c via PCA9306 - u45 */
356	i2c-mux@74 { /* u34 */
357		compatible = "nxp,pca9548";
358		#address-cells = <1>;
359		#size-cells = <0>;
360		reg = <0x74>;
361		i2c@0 {
362			#address-cells = <1>;
363			#size-cells = <0>;
364			reg = <0>;
365			/*
366			 * IIC_EEPROM 1kB memory which uses 256B blocks
367			 * where every block has different address.
368			 *    0 - 256B address 0x54
369			 * 256B - 512B address 0x55
370			 * 512B - 768B address 0x56
371			 * 768B - 1024B address 0x57
372			 */
373			eeprom: eeprom@54 { /* u23 */
374				compatible = "atmel,24c08";
375				reg = <0x54>;
376			};
377		};
378		i2c@1 {
379			#address-cells = <1>;
380			#size-cells = <0>;
381			reg = <1>;
382			si5341: clock-generator@36 { /* SI5341 - u69 */
383				compatible = "si5341";
384				reg = <0x36>;
385			};
386
387		};
388		i2c@2 {
389			#address-cells = <1>;
390			#size-cells = <0>;
391			reg = <2>;
392			si570_1: clock-generator@5d { /* USER SI570 - u42 */
393				#clock-cells = <0>;
394				compatible = "silabs,si570";
395				reg = <0x5d>;
396				temperature-stability = <50>;
397				factory-fout = <300000000>;
398				clock-frequency = <300000000>;
399				clock-output-names = "si570_user";
400			};
401		};
402		i2c@3 {
403			#address-cells = <1>;
404			#size-cells = <0>;
405			reg = <3>;
406			si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
407				#clock-cells = <0>;
408				compatible = "silabs,si570";
409				reg = <0x5d>;
410				temperature-stability = <50>; /* copy from zc702 */
411				factory-fout = <156250000>;
412				clock-frequency = <148500000>;
413				clock-output-names = "si570_mgt";
414			};
415		};
416		i2c@4 {
417			#address-cells = <1>;
418			#size-cells = <0>;
419			reg = <4>;
420			si5328: clock-generator@69 {/* SI5328 - u20 */
421				compatible = "silabs,si5328";
422				reg = <0x69>;
423			};
424		};
425		i2c@5 {
426			#address-cells = <1>;
427			#size-cells = <0>;
428			reg = <5>; /* FAN controller */
429			temp@4c {/* lm96163 - u128 */
430				compatible = "national,lm96163";
431				reg = <0x4c>;
432			};
433		};
434		/* 6 - 7 unconnected */
435	};
436
437	i2c-mux@75 {
438		compatible = "nxp,pca9548"; /* u135 */
439		#address-cells = <1>;
440		#size-cells = <0>;
441		reg = <0x75>;
442
443		i2c@0 {
444			#address-cells = <1>;
445			#size-cells = <0>;
446			reg = <0>;
447			/* HPC0_IIC */
448		};
449		i2c@1 {
450			#address-cells = <1>;
451			#size-cells = <0>;
452			reg = <1>;
453			/* HPC1_IIC */
454		};
455		i2c@2 {
456			#address-cells = <1>;
457			#size-cells = <0>;
458			reg = <2>;
459			/* SYSMON */
460		};
461		i2c@3 {
462			#address-cells = <1>;
463			#size-cells = <0>;
464			reg = <3>;
465			/* DDR4 SODIMM */
466		};
467		i2c@4 {
468			#address-cells = <1>;
469			#size-cells = <0>;
470			reg = <4>;
471			/* SEP 3 */
472		};
473		i2c@5 {
474			#address-cells = <1>;
475			#size-cells = <0>;
476			reg = <5>;
477			/* SEP 2 */
478		};
479		i2c@6 {
480			#address-cells = <1>;
481			#size-cells = <0>;
482			reg = <6>;
483			/* SEP 1 */
484		};
485		i2c@7 {
486			#address-cells = <1>;
487			#size-cells = <0>;
488			reg = <7>;
489			/* SEP 0 */
490		};
491	};
492};
493
494&qspi {
495	status = "okay";
496	is-dual = <1>;
497	flash@0 {
498		compatible = "m25p80", "spi-flash"; /* 32MB */
499		#address-cells = <1>;
500		#size-cells = <1>;
501		reg = <0x0>;
502		spi-tx-bus-width = <1>;
503		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
504		spi-max-frequency = <108000000>; /* Based on DC1 spec */
505		partition@qspi-fsbl-uboot { /* for testing purpose */
506			label = "qspi-fsbl-uboot";
507			reg = <0x0 0x100000>;
508		};
509		partition@qspi-linux { /* for testing purpose */
510			label = "qspi-linux";
511			reg = <0x100000 0x500000>;
512		};
513		partition@qspi-device-tree { /* for testing purpose */
514			label = "qspi-device-tree";
515			reg = <0x600000 0x20000>;
516		};
517		partition@qspi-rootfs { /* for testing purpose */
518			label = "qspi-rootfs";
519			reg = <0x620000 0x5E0000>;
520		};
521	};
522};
523
524&rtc {
525	status = "okay";
526};
527
528&sata {
529	status = "okay";
530	/* SATA OOB timing settings */
531	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
532	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
533	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
534	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
535	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
536	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
537	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
538	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
539	phy-names = "sata-phy";
540	phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
541};
542
543/* SD1 with level shifter */
544&sdhci1 {
545	status = "okay";
546	no-1-8-v;
547	xlnx,mio_bank = <1>;
548};
549
550&serdes {
551	status = "okay";
552};
553
554&uart0 {
555	status = "okay";
556};
557
558&uart1 {
559	status = "okay";
560};
561
562/* ULPI SMSC USB3320 */
563&usb0 {
564	status = "okay";
565};
566
567&dwc3_0 {
568	status = "okay";
569	dr_mode = "host";
570	snps,usb3_lpm_capable;
571	phy-names = "usb3-phy";
572	phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
573};
574
575&watchdog0 {
576	status = "okay";
577};
578