1/*
2 * dts file for Xilinx ZynqMP ZCU102 RevA
3 *
4 * (C) Copyright 2015, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * SPDX-License-Identifier:	GPL-2.0+
9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk.dtsi"
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17
18/ {
19	model = "ZynqMP ZCU102 RevA";
20	compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
21
22	aliases {
23		ethernet0 = &gem3;
24		gpio0 = &gpio;
25		i2c0 = &i2c0;
26		i2c1 = &i2c1;
27		mmc0 = &sdhci1;
28		rtc0 = &rtc;
29		serial0 = &uart0;
30		serial1 = &uart1;
31		serial2 = &dcc;
32		spi0 = &qspi;
33		usb0 = &usb0;
34	};
35
36	chosen {
37		bootargs = "earlycon";
38		stdout-path = "serial0:115200n8";
39	};
40
41	memory@0 {
42		device_type = "memory";
43		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
44	};
45
46	gpio-keys {
47		compatible = "gpio-keys";
48		#address-cells = <1>;
49		#size-cells = <0>;
50		autorepeat;
51		sw19 {
52			label = "sw19";
53			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
54			linux,code = <108>; /* down */
55			gpio-key,wakeup;
56			autorepeat;
57		};
58	};
59
60	leds {
61		compatible = "gpio-leds";
62		heartbeat_led {
63			label = "heartbeat";
64			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
65			linux,default-trigger = "heartbeat";
66		};
67	};
68};
69
70&can1 {
71	status = "okay";
72	pinctrl-names = "default";
73	pinctrl-0 = <&pinctrl_can1_default>;
74};
75
76&dcc {
77	status = "okay";
78};
79
80/* fpd_dma clk 667MHz, lpd_dma 500MHz */
81&fpd_dma_chan1 {
82	status = "okay";
83	xlnx,include-sg; /* for testing purpose */
84	xlnx,overfetch; /* for testing purpose */
85	xlnx,ratectrl = <0>; /* for testing purpose */
86	xlnx,src-issue = <31>;
87};
88
89&fpd_dma_chan2 {
90	status = "okay";
91	xlnx,ratectrl = <100>; /* for testing purpose */
92	xlnx,src-issue = <4>; /* for testing purpose */
93};
94
95&fpd_dma_chan3 {
96	status = "okay";
97};
98
99&fpd_dma_chan4 {
100	status = "okay";
101	xlnx,include-sg; /* for testing purpose */
102};
103
104&fpd_dma_chan5 {
105	status = "okay";
106};
107
108&fpd_dma_chan6 {
109	status = "okay";
110	xlnx,include-sg; /* for testing purpose */
111};
112
113&fpd_dma_chan7 {
114	status = "okay";
115};
116
117&fpd_dma_chan8 {
118	status = "okay";
119	xlnx,include-sg; /* for testing purpose */
120};
121
122&gem3 {
123	status = "okay";
124	phy-handle = <&phy0>;
125	phy-mode = "rgmii-id";
126	pinctrl-names = "default";
127	pinctrl-0 = <&pinctrl_gem3_default>;
128	phy0: phy@21 {
129		reg = <21>;
130		ti,rx-internal-delay = <0x8>;
131		ti,tx-internal-delay = <0xa>;
132		ti,fifo-depth = <0x1>;
133	};
134};
135
136&gpio {
137	status = "okay";
138	pinctrl-names = "default";
139	pinctrl-0 = <&pinctrl_gpio_default>;
140};
141
142&gpu {
143	status = "okay";
144};
145
146&i2c0 {
147	status = "okay";
148	clock-frequency = <400000>;
149	pinctrl-names = "default", "gpio";
150	pinctrl-0 = <&pinctrl_i2c0_default>;
151	pinctrl-1 = <&pinctrl_i2c0_gpio>;
152	scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
153	sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
154
155	tca6416_u97: gpio@20 {
156		/*
157		 * Enable all GTs to out from U-Boot
158		 * i2c mw 20 6 0  - setup IO to output
159		 * i2c mw 20 2 ef - setup output values on pins 0-7
160		 * i2c mw 20 3 ff - setup output values on pins 10-17
161		 */
162		compatible = "ti,tca6416";
163		reg = <0x20>;
164		gpio-controller;
165		#gpio-cells = <2>;
166		/*
167		 * IRQ not connected
168		 * Lines:
169		 * 0 - PS_GTR_LAN_SEL0
170		 * 1 - PS_GTR_LAN_SEL1
171		 * 2 - PS_GTR_LAN_SEL2
172		 * 3 - PS_GTR_LAN_SEL3
173		 * 4 - PCI_CLK_DIR_SEL
174		 * 5 - IIC_MUX_RESET_B
175		 * 6 - GEM3_EXP_RESET_B
176		 * 7, 10 - 17 - not connected
177		 */
178
179		gtr_sel0 {
180			gpio-hog;
181			gpios = <0 0>;
182			output-low; /* PCIE = 0, DP = 1 */
183			line-name = "sel0";
184		};
185		gtr_sel1 {
186			gpio-hog;
187			gpios = <1 0>;
188			output-high; /* PCIE = 0, DP = 1 */
189			line-name = "sel1";
190		};
191		gtr_sel2 {
192			gpio-hog;
193			gpios = <2 0>;
194			output-high; /* PCIE = 0, USB0 = 1 */
195			line-name = "sel2";
196		};
197		gtr_sel3 {
198			gpio-hog;
199			gpios = <3 0>;
200			output-high; /* PCIE = 0, SATA = 1 */
201			line-name = "sel3";
202		};
203	};
204
205	tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
206		compatible = "ti,tca6416";
207		reg = <0x21>;
208		gpio-controller;
209		#gpio-cells = <2>;
210		/*
211		 * IRQ not connected
212		 * Lines:
213		 * 0 - VCCPSPLL_EN
214		 * 1 - MGTRAVCC_EN
215		 * 2 - MGTRAVTT_EN
216		 * 3 - VCCPSDDRPLL_EN
217		 * 4 - MIO26_PMU_INPUT_LS
218		 * 5 - PL_PMBUS_ALERT
219		 * 6 - PS_PMBUS_ALERT
220		 * 7 - MAXIM_PMBUS_ALERT
221		 * 10 - PL_DDR4_VTERM_EN
222		 * 11 - PL_DDR4_VPP_2V5_EN
223		 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
224		 * 13 - PS_DIMM_SUSPEND_EN
225		 * 14 - PS_DDR4_VTERM_EN
226		 * 15 - PS_DDR4_VPP_2V5_EN
227		 * 16 - 17 - not connected
228		 */
229	};
230
231	i2cswitch@75 { /* u60 */
232		compatible = "nxp,pca9544";
233		#address-cells = <1>;
234		#size-cells = <0>;
235		reg = <0x75>;
236		i2c@0 { /* i2c mw 75 0 1 */
237			#address-cells = <1>;
238			#size-cells = <0>;
239			reg = <0>;
240			/* PS_PMBUS */
241			ina226@40 { /* u76 */
242				compatible = "ti,ina226";
243				reg = <0x40>;
244				shunt-resistor = <5000>;
245			};
246			ina226@41 { /* u77 */
247				compatible = "ti,ina226";
248				reg = <0x41>;
249				shunt-resistor = <5000>;
250			};
251			ina226@42 { /* u78 */
252				compatible = "ti,ina226";
253				reg = <0x42>;
254				shunt-resistor = <5000>;
255			};
256			ina226@43 { /* u87 */
257				compatible = "ti,ina226";
258				reg = <0x43>;
259				shunt-resistor = <5000>;
260			};
261			ina226@44 { /* u85 */
262				compatible = "ti,ina226";
263				reg = <0x44>;
264				shunt-resistor = <5000>;
265			};
266			ina226@45 { /* u86 */
267				compatible = "ti,ina226";
268				reg = <0x45>;
269				shunt-resistor = <5000>;
270			};
271			ina226@46 { /* u93 */
272				compatible = "ti,ina226";
273				reg = <0x46>;
274				shunt-resistor = <5000>;
275			};
276			ina226@47 { /* u88 */
277				compatible = "ti,ina226";
278				reg = <0x47>;
279				shunt-resistor = <5000>;
280			};
281			ina226@4a { /* u15 */
282				compatible = "ti,ina226";
283				reg = <0x4a>;
284				shunt-resistor = <5000>;
285			};
286			ina226@4b { /* u92 */
287				compatible = "ti,ina226";
288				reg = <0x4b>;
289				shunt-resistor = <5000>;
290			};
291		};
292		i2c@1 { /* i2c mw 75 0 1 */
293			#address-cells = <1>;
294			#size-cells = <0>;
295			reg = <1>;
296			/* PL_PMBUS */
297			ina226@40 { /* u79 */
298				compatible = "ti,ina226";
299				reg = <0x40>;
300				shunt-resistor = <2000>;
301			};
302			ina226@41 { /* u81 */
303				compatible = "ti,ina226";
304				reg = <0x41>;
305				shunt-resistor = <5000>;
306			};
307			ina226@42 { /* u80 */
308				compatible = "ti,ina226";
309				reg = <0x42>;
310				shunt-resistor = <5000>;
311			};
312			ina226@43 { /* u84 */
313				compatible = "ti,ina226";
314				reg = <0x43>;
315				shunt-resistor = <5000>;
316			};
317			ina226@44 { /* u16 */
318				compatible = "ti,ina226";
319				reg = <0x44>;
320				shunt-resistor = <5000>;
321			};
322			ina226@45 { /* u65 */
323				compatible = "ti,ina226";
324				reg = <0x45>;
325				shunt-resistor = <5000>;
326			};
327			ina226@46 { /* u74 */
328				compatible = "ti,ina226";
329				reg = <0x46>;
330				shunt-resistor = <5000>;
331			};
332			ina226@47 { /* u75 */
333				compatible = "ti,ina226";
334				reg = <0x47>;
335				shunt-resistor = <5000>;
336			};
337		};
338		i2c@2 { /* i2c mw 75 0 1 */
339			#address-cells = <1>;
340			#size-cells = <0>;
341			reg = <2>;
342			/* MAXIM_PMBUS - 00 */
343			max15301@a { /* u46 */
344				compatible = "max15301";
345				reg = <0xa>;
346			};
347			max15303@b { /* u4 */
348				compatible = "max15303";
349				reg = <0xb>;
350			};
351			max15303@10 { /* u13 */
352				compatible = "max15303";
353				reg = <0x10>;
354			};
355			max15301@13 { /* u47 */
356				compatible = "max15301";
357				reg = <0x13>;
358			};
359			max15303@14 { /* u7 */
360				compatible = "max15303";
361				reg = <0x14>;
362			};
363			max15303@15 { /* u6 */
364				compatible = "max15303";
365				reg = <0x15>;
366			};
367			max15303@16 { /* u10 */
368				compatible = "max15303";
369				reg = <0x16>;
370			};
371			max15303@17 { /* u9 */
372				compatible = "max15303";
373				reg = <0x17>;
374			};
375			max15301@18 { /* u63 */
376				compatible = "max15301";
377				reg = <0x18>;
378			};
379			max15303@1a { /* u49 */
380				compatible = "max15303";
381				reg = <0x1a>;
382			};
383			max15303@1d { /* u18 */
384				compatible = "max15303";
385				reg = <0x1d>;
386			};
387			max15303@20 { /* u8 */
388				compatible = "max15303";
389				status = "disabled"; /* unreachable */
390				reg = <0x20>;
391			};
392
393/*			drivers/hwmon/pmbus/Kconfig:86:   be called max20751.
394drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
395*/
396			max20751@72 { /* u95 FIXME - not detected */
397				compatible = "max20751";
398				reg = <0x72>;
399			};
400			max20751@73 { /* u96 FIXME - not detected */
401				compatible = "max20751";
402				reg = <0x73>;
403			};
404		};
405		/* Bus 3 is not connected */
406	};
407
408	/* FIXME PMOD - j160 */
409	/* FIXME MSP430F - u41 - not detected */
410};
411
412&i2c1 {
413	status = "okay";
414	clock-frequency = <400000>;
415	pinctrl-names = "default", "gpio";
416	pinctrl-0 = <&pinctrl_i2c1_default>;
417	pinctrl-1 = <&pinctrl_i2c1_gpio>;
418	scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
419	sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
420
421	/* FIXME PL i2c via PCA9306 - u45 */
422	/* FIXME MSP430 - u41 - not detected */
423	i2cswitch@74 { /* u34 */
424		compatible = "nxp,pca9548";
425		#address-cells = <1>;
426		#size-cells = <0>;
427		reg = <0x74>;
428		i2c@0 { /* i2c mw 74 0 1 */
429			#address-cells = <1>;
430			#size-cells = <0>;
431			reg = <0>;
432			/*
433			 * IIC_EEPROM 1kB memory which uses 256B blocks
434			 * where every block has different address.
435			 *    0 - 256B address 0x54
436			 * 256B - 512B address 0x55
437			 * 512B - 768B address 0x56
438			 * 768B - 1024B address 0x57
439			 */
440			eeprom: eeprom@54 { /* u23 */
441				compatible = "at,24c08";
442				reg = <0x54>;
443			};
444		};
445		i2c@1 { /* i2c mw 74 0 2 */
446			#address-cells = <1>;
447			#size-cells = <0>;
448			reg = <1>;
449			si5341: clock-generator1@36 { /* SI5341 - u69 */
450				compatible = "si5341";
451				reg = <0x36>;
452			};
453
454		};
455		i2c@2 { /* i2c mw 74 0 4 */
456			#address-cells = <1>;
457			#size-cells = <0>;
458			reg = <2>;
459			si570_1: clock-generator2@5d { /* USER SI570 - u42 */
460				#clock-cells = <0>;
461				compatible = "silabs,si570";
462				reg = <0x5d>;
463				temperature-stability = <50>;
464				factory-fout = <300000000>;
465				clock-frequency = <300000000>;
466			};
467		};
468		i2c@3 { /* i2c mw 74 0 8 */
469			#address-cells = <1>;
470			#size-cells = <0>;
471			reg = <3>;
472			si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
473				#clock-cells = <0>;
474				compatible = "silabs,si570";
475				reg = <0x5d>;
476				temperature-stability = <50>; /* copy from zc702 */
477				factory-fout = <156250000>;
478				clock-frequency = <148500000>;
479			};
480		};
481		i2c@4 { /* i2c mw 74 0 10 */
482			#address-cells = <1>;
483			#size-cells = <0>;
484			reg = <4>;
485			si5328: clock-generator4@69 {/* SI5328 - u20 */
486				compatible = "silabs,si5328";
487				reg = <0x69>;
488				/*
489				 * Chip has interrupt present connected to PL
490				 * interrupt-parent = <&>;
491				 * interrupts = <>;
492				 */
493			};
494		};
495		/* 5 - 7 unconnected */
496	};
497
498	i2cswitch@75 {
499		compatible = "nxp,pca9548"; /* u135 */
500		#address-cells = <1>;
501		#size-cells = <0>;
502		reg = <0x75>;
503
504		i2c@0 {
505			#address-cells = <1>;
506			#size-cells = <0>;
507			reg = <0>;
508			/* HPC0_IIC */
509		};
510		i2c@1 {
511			#address-cells = <1>;
512			#size-cells = <0>;
513			reg = <1>;
514			/* HPC1_IIC */
515		};
516		i2c@2 {
517			#address-cells = <1>;
518			#size-cells = <0>;
519			reg = <2>;
520			/* SYSMON */
521		};
522		i2c@3 { /* i2c mw 75 0 8 */
523			#address-cells = <1>;
524			#size-cells = <0>;
525			reg = <3>;
526			/* DDR4 SODIMM */
527			dev@19 { /* u-boot detection */
528				compatible = "xxx";
529				reg = <0x19>;
530			};
531			dev@30 { /* u-boot detection */
532				compatible = "xxx";
533				reg = <0x30>;
534			};
535			dev@35 { /* u-boot detection */
536				compatible = "xxx";
537				reg = <0x35>;
538			};
539			dev@36 { /* u-boot detection */
540				compatible = "xxx";
541				reg = <0x36>;
542			};
543			dev@51 { /* u-boot detection - maybe SPD */
544				compatible = "xxx";
545				reg = <0x51>;
546			};
547		};
548		i2c@4 {
549			#address-cells = <1>;
550			#size-cells = <0>;
551			reg = <4>;
552			/* SEP 3 */
553		};
554		i2c@5 {
555			#address-cells = <1>;
556			#size-cells = <0>;
557			reg = <5>;
558			/* SEP 2 */
559		};
560		i2c@6 {
561			#address-cells = <1>;
562			#size-cells = <0>;
563			reg = <6>;
564			/* SEP 1 */
565		};
566		i2c@7 {
567			#address-cells = <1>;
568			#size-cells = <0>;
569			reg = <7>;
570			/* SEP 0 */
571		};
572	};
573};
574
575&pinctrl0 {
576	status = "okay";
577	pinctrl_i2c0_default: i2c0-default {
578		mux {
579			groups = "i2c0_3_grp";
580			function = "i2c0";
581		};
582
583		conf {
584			groups = "i2c0_3_grp";
585			bias-pull-up;
586			slew-rate = <SLEW_RATE_SLOW>;
587			io-standard = <IO_STANDARD_LVCMOS18>;
588		};
589	};
590
591	pinctrl_i2c0_gpio: i2c0-gpio {
592		mux {
593			groups = "gpio0_14_grp", "gpio0_15_grp";
594			function = "gpio0";
595		};
596
597		conf {
598			groups = "gpio0_14_grp", "gpio0_15_grp";
599			slew-rate = <SLEW_RATE_SLOW>;
600			io-standard = <IO_STANDARD_LVCMOS18>;
601		};
602	};
603
604	pinctrl_i2c1_default: i2c1-default {
605		mux {
606			groups = "i2c1_4_grp";
607			function = "i2c1";
608		};
609
610		conf {
611			groups = "i2c1_4_grp";
612			bias-pull-up;
613			slew-rate = <SLEW_RATE_SLOW>;
614			io-standard = <IO_STANDARD_LVCMOS18>;
615		};
616	};
617
618	pinctrl_i2c1_gpio: i2c1-gpio {
619		mux {
620			groups = "gpio0_16_grp", "gpio0_17_grp";
621			function = "gpio0";
622		};
623
624		conf {
625			groups = "gpio0_16_grp", "gpio0_17_grp";
626			slew-rate = <SLEW_RATE_SLOW>;
627			io-standard = <IO_STANDARD_LVCMOS18>;
628		};
629	};
630
631	pinctrl_uart0_default: uart0-default {
632		mux {
633			groups = "uart0_4_grp";
634			function = "uart0";
635		};
636
637		conf {
638			groups = "uart0_4_grp";
639			slew-rate = <SLEW_RATE_SLOW>;
640			io-standard = <IO_STANDARD_LVCMOS18>;
641		};
642
643		conf-rx {
644			pins = "MIO18";
645			bias-high-impedance;
646		};
647
648		conf-tx {
649			pins = "MIO19";
650			bias-disable;
651		};
652	};
653
654	pinctrl_uart1_default: uart1-default {
655		mux {
656			groups = "uart1_5_grp";
657			function = "uart1";
658		};
659
660		conf {
661			groups = "uart1_5_grp";
662			slew-rate = <SLEW_RATE_SLOW>;
663			io-standard = <IO_STANDARD_LVCMOS18>;
664		};
665
666		conf-rx {
667			pins = "MIO21";
668			bias-high-impedance;
669		};
670
671		conf-tx {
672			pins = "MIO20";
673			bias-disable;
674		};
675	};
676
677	pinctrl_usb0_default: usb0-default {
678		mux {
679			groups = "usb0_0_grp";
680			function = "usb0";
681		};
682
683		conf {
684			groups = "usb0_0_grp";
685			slew-rate = <SLEW_RATE_SLOW>;
686			io-standard = <IO_STANDARD_LVCMOS18>;
687		};
688
689		conf-rx {
690			pins = "MIO52", "MIO53", "MIO55";
691			bias-high-impedance;
692		};
693
694		conf-tx {
695			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
696			       "MIO60", "MIO61", "MIO62", "MIO63";
697			bias-disable;
698		};
699	};
700
701	pinctrl_gem3_default: gem3-default {
702		mux {
703			function = "ethernet3";
704			groups = "ethernet3_0_grp";
705		};
706
707		conf {
708			groups = "ethernet3_0_grp";
709			slew-rate = <SLEW_RATE_SLOW>;
710			io-standard = <IO_STANDARD_LVCMOS18>;
711		};
712
713		conf-rx {
714			pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
715									"MIO75";
716			bias-high-impedance;
717			low-power-disable;
718		};
719
720		conf-tx {
721			pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
722									"MIO69";
723			bias-disable;
724			low-power-enable;
725		};
726
727		mux-mdio {
728			function = "mdio3";
729			groups = "mdio3_0_grp";
730		};
731
732		conf-mdio {
733			groups = "mdio3_0_grp";
734			slew-rate = <SLEW_RATE_SLOW>;
735			io-standard = <IO_STANDARD_LVCMOS18>;
736			bias-disable;
737		};
738	};
739
740	pinctrl_can1_default: can1-default {
741		mux {
742			function = "can1";
743			groups = "can1_6_grp";
744		};
745
746		conf {
747			groups = "can1_6_grp";
748			slew-rate = <SLEW_RATE_SLOW>;
749			io-standard = <IO_STANDARD_LVCMOS18>;
750		};
751
752		conf-rx {
753			pins = "MIO25";
754			bias-high-impedance;
755		};
756
757		conf-tx {
758			pins = "MIO24";
759			bias-disable;
760		};
761	};
762
763	pinctrl_sdhci1_default: sdhci1-default {
764		mux {
765			groups = "sdio1_0_grp";
766			function = "sdio1";
767		};
768
769		conf {
770			groups = "sdio1_0_grp";
771			slew-rate = <SLEW_RATE_SLOW>;
772			io-standard = <IO_STANDARD_LVCMOS18>;
773			bias-disable;
774		};
775
776		mux-cd {
777			groups = "sdio1_0_cd_grp";
778			function = "sdio1_cd";
779		};
780
781		conf-cd {
782			groups = "sdio1_0_cd_grp";
783			bias-high-impedance;
784			bias-pull-up;
785			slew-rate = <SLEW_RATE_SLOW>;
786			io-standard = <IO_STANDARD_LVCMOS18>;
787		};
788
789		mux-wp {
790			groups = "sdio1_0_wp_grp";
791			function = "sdio1_wp";
792		};
793
794		conf-wp {
795			groups = "sdio1_0_wp_grp";
796			bias-high-impedance;
797			bias-pull-up;
798			slew-rate = <SLEW_RATE_SLOW>;
799			io-standard = <IO_STANDARD_LVCMOS18>;
800		};
801	};
802
803	pinctrl_gpio_default: gpio-default {
804		mux-sw {
805			function = "gpio0";
806			groups = "gpio0_22_grp", "gpio0_23_grp";
807		};
808
809		conf-sw {
810			groups = "gpio0_22_grp", "gpio0_23_grp";
811			slew-rate = <SLEW_RATE_SLOW>;
812			io-standard = <IO_STANDARD_LVCMOS18>;
813		};
814
815		mux-msp {
816			function = "gpio0";
817			groups = "gpio0_13_grp", "gpio0_38_grp";
818		};
819
820		conf-msp {
821			groups = "gpio0_13_grp", "gpio0_38_grp";
822			slew-rate = <SLEW_RATE_SLOW>;
823			io-standard = <IO_STANDARD_LVCMOS18>;
824		};
825
826		conf-pull-up {
827			pins = "MIO22", "MIO23";
828			bias-pull-up;
829		};
830
831		conf-pull-none {
832			pins = "MIO13", "MIO38";
833			bias-disable;
834		};
835	};
836};
837
838&pcie {
839	status = "okay";
840};
841
842&qspi {
843	status = "okay";
844	is-dual = <1>;
845	flash@0 {
846		compatible = "m25p80"; /* 32MB */
847		#address-cells = <1>;
848		#size-cells = <1>;
849		reg = <0x0>;
850		spi-tx-bus-width = <1>;
851		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
852		spi-max-frequency = <108000000>; /* Based on DC1 spec */
853		partition@qspi-fsbl-uboot { /* for testing purpose */
854			label = "qspi-fsbl-uboot";
855			reg = <0x0 0x100000>;
856		};
857		partition@qspi-linux { /* for testing purpose */
858			label = "qspi-linux";
859			reg = <0x100000 0x500000>;
860		};
861		partition@qspi-device-tree { /* for testing purpose */
862			label = "qspi-device-tree";
863			reg = <0x600000 0x20000>;
864		};
865		partition@qspi-rootfs { /* for testing purpose */
866			label = "qspi-rootfs";
867			reg = <0x620000 0x5E0000>;
868		};
869	};
870};
871
872&rtc {
873	status = "okay";
874};
875
876&sata {
877	status = "okay";
878	/* SATA OOB timing settings */
879	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
880	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
881	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
882	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
883	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
884	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
885	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
886	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
887};
888
889/* SD1 with level shifter */
890&sdhci1 {
891	status = "okay";
892	pinctrl-names = "default";
893	pinctrl-0 = <&pinctrl_sdhci1_default>;
894	no-1-8-v;	/* for 1.0 silicon */
895	xlnx,mio_bank = <1>;
896};
897
898&uart0 {
899	status = "okay";
900	pinctrl-names = "default";
901	pinctrl-0 = <&pinctrl_uart0_default>;
902};
903
904&uart1 {
905	status = "okay";
906	pinctrl-names = "default";
907	pinctrl-0 = <&pinctrl_uart1_default>;
908};
909
910/* ULPI SMSC USB3320 */
911&usb0 {
912	status = "okay";
913	pinctrl-names = "default";
914	pinctrl-0 = <&pinctrl_usb0_default>;
915};
916
917&dwc3_0 {
918	status = "okay";
919	dr_mode = "host";
920};
921
922&watchdog0 {
923	status = "okay";
924};
925
926&xilinx_ams {
927	status = "okay";
928};
929
930&ams_ps {
931	status = "okay";
932};
933
934&ams_pl {
935	status = "okay";
936};
937
938&xilinx_drm {
939	status = "okay";
940	clocks = <&si570_1>;
941};
942
943&xlnx_dp {
944	status = "okay";
945};
946
947&xlnx_dp_sub {
948	status = "okay";
949	xlnx,vid-clk-pl;
950};
951
952&xlnx_dp_snd_pcm0 {
953	status = "okay";
954};
955
956&xlnx_dp_snd_pcm1 {
957	status = "okay";
958};
959
960&xlnx_dp_snd_card {
961	status = "okay";
962};
963
964&xlnx_dp_snd_codec0 {
965	status = "okay";
966};
967
968&xlnx_dpdma {
969	status = "okay";
970};
971