1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
4 *
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
6 *
7 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
8 * Michal Simek <michal.simek@xilinx.com>
9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk-ccf.dtsi"
15/ {
16	model = "ZynqMP zc1751-xm019-dc5 RevA";
17	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
18
19	aliases {
20		ethernet0 = &gem1;
21		gpio0 = &gpio;
22		i2c0 = &i2c0;
23		i2c1 = &i2c1;
24		mmc0 = &sdhci0;
25		serial0 = &uart0;
26		serial1 = &uart1;
27	};
28
29	chosen {
30		bootargs = "earlycon";
31		stdout-path = "serial0:115200n8";
32	};
33
34	memory@0 {
35		device_type = "memory";
36		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
37	};
38};
39
40&fpd_dma_chan1 {
41	status = "okay";
42};
43
44&fpd_dma_chan2 {
45	status = "okay";
46};
47
48&fpd_dma_chan3 {
49	status = "okay";
50};
51
52&fpd_dma_chan4 {
53	status = "okay";
54};
55
56&fpd_dma_chan5 {
57	status = "okay";
58};
59
60&fpd_dma_chan6 {
61	status = "okay";
62};
63
64&fpd_dma_chan7 {
65	status = "okay";
66};
67
68&fpd_dma_chan8 {
69	status = "okay";
70};
71
72&gem1 {
73	status = "okay";
74	phy-handle = <&phy0>;
75	phy-mode = "rgmii-id";
76	phy0: phy@0 {
77		reg = <0>;
78	};
79};
80
81&gpio {
82	status = "okay";
83};
84
85&i2c0 {
86	status = "okay";
87};
88
89&i2c1 {
90	status = "okay";
91};
92
93&sdhci0 {
94	status = "okay";
95	no-1-8-v;
96};
97
98&ttc0 {
99	status = "okay";
100};
101
102&ttc1 {
103	status = "okay";
104};
105
106&ttc2 {
107	status = "okay";
108};
109
110&ttc3 {
111	status = "okay";
112};
113
114&uart0 {
115	status = "okay";
116};
117
118&uart1 {
119	status = "okay";
120};
121
122&watchdog0 {
123	status = "okay";
124};
125