1/*
2 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
3 *
4 * (C) Copyright 2015 - 2016, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * SPDX-License-Identifier:	GPL-2.0+
9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk.dtsi"
15
16/ {
17	model = "ZynqMP zc1751-xm018-dc4";
18	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
19
20	aliases {
21		can0 = &can0;
22		can1 = &can1;
23		ethernet0 = &gem0;
24		ethernet1 = &gem1;
25		ethernet2 = &gem2;
26		ethernet3 = &gem3;
27		gpio0 = &gpio;
28		i2c0 = &i2c0;
29		i2c1 = &i2c1;
30		rtc0 = &rtc;
31		serial0 = &uart0;
32		serial1 = &uart1;
33		spi0 = &qspi;
34	};
35
36	chosen {
37		bootargs = "earlycon";
38		stdout-path = "serial0:115200n8";
39	};
40
41	memory@0 {
42		device_type = "memory";
43		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
44	};
45};
46
47&can0 {
48	status = "okay";
49};
50
51&can1 {
52	status = "okay";
53};
54
55/* fpd_dma clk 667MHz, lpd_dma 500MHz */
56&fpd_dma_chan1 {
57	status = "okay";
58};
59
60&fpd_dma_chan2 {
61	status = "okay";
62};
63
64&fpd_dma_chan3 {
65	status = "okay";
66};
67
68&fpd_dma_chan4 {
69	status = "okay";
70};
71
72&fpd_dma_chan5 {
73	status = "okay";
74};
75
76&fpd_dma_chan6 {
77	status = "okay";
78};
79
80&fpd_dma_chan7 {
81	status = "okay";
82};
83
84&fpd_dma_chan8 {
85	status = "okay";
86};
87
88&lpd_dma_chan1 {
89	status = "okay";
90};
91
92&lpd_dma_chan2 {
93	status = "okay";
94};
95
96&lpd_dma_chan3 {
97	status = "okay";
98};
99
100&lpd_dma_chan4 {
101	status = "okay";
102};
103
104&lpd_dma_chan5 {
105	status = "okay";
106};
107
108&lpd_dma_chan6 {
109	status = "okay";
110};
111
112&lpd_dma_chan7 {
113	status = "okay";
114};
115
116&lpd_dma_chan8 {
117	status = "okay";
118};
119
120&xlnx_dp {
121	status = "okay";
122};
123
124&xlnx_dpdma {
125	status = "okay";
126};
127
128&gem0 {
129	status = "okay";
130	phy-mode = "rgmii-id";
131	phy-handle = <&ethernet_phy0>;
132	ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
133		reg = <0>;
134	};
135	ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
136		reg = <7>;
137	};
138	ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
139		reg = <3>;
140	};
141	ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
142		reg = <8>;
143	};
144};
145
146&gem1 {
147	status = "okay";
148	phy-mode = "rgmii-id";
149	phy-handle = <&ethernet_phy7>;
150};
151
152&gem2 {
153	status = "okay";
154	phy-mode = "rgmii-id";
155	phy-handle = <&ethernet_phy3>;
156};
157
158&gem3 {
159	status = "okay";
160	phy-mode = "rgmii-id";
161	phy-handle = <&ethernet_phy8>;
162};
163
164&gpio {
165	status = "okay";
166};
167
168&gpu {
169	status = "okay";
170};
171
172&i2c0 {
173	clock-frequency = <400000>;
174	status = "okay";
175};
176
177&i2c1 {
178	clock-frequency = <400000>;
179	status = "okay";
180};
181
182&rtc {
183	status = "okay";
184};
185
186&uart0 {
187	status = "okay";
188};
189
190&uart1 {
191	status = "okay";
192};
193
194&watchdog0 {
195	status = "okay";
196};
197