1/*
2 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
3 *
4 * (C) Copyright 2015 - 2016, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 */
13
14/dts-v1/;
15
16#include "zynqmp.dtsi"
17#include "zynqmp-clk.dtsi"
18
19/ {
20	model = "ZynqMP zc1751-xm018-dc4";
21	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
22
23	aliases {
24		can0 = &can0;
25		can1 = &can1;
26		ethernet0 = &gem0;
27		ethernet1 = &gem1;
28		ethernet2 = &gem2;
29		ethernet3 = &gem3;
30		gpio0 = &gpio;
31		i2c0 = &i2c0;
32		i2c1 = &i2c1;
33		rtc0 = &rtc;
34		serial0 = &uart0;
35		serial1 = &uart1;
36		spi0 = &qspi;
37	};
38
39	chosen {
40		bootargs = "earlycon";
41		stdout-path = "serial0:115200n8";
42	};
43
44	memory {
45		device_type = "memory";
46		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
47	};
48};
49
50&can0 {
51	status = "okay";
52};
53
54&can1 {
55	status = "okay";
56};
57
58/* fpd_dma clk 667MHz, lpd_dma 500MHz */
59&fpd_dma_chan1 {
60	status = "okay";
61	xlnx,include-sg; /* for testing purpose */
62	xlnx,overfetch; /* for testing purpose */
63	xlnx,ratectrl = <0>; /* for testing purpose */
64	xlnx,src-issue = <31>;
65};
66
67&fpd_dma_chan2 {
68	status = "okay";
69	xlnx,ratectrl = <100>; /* for testing purpose */
70	xlnx,src-issue = <4>; /* for testing purpose */
71};
72
73&fpd_dma_chan3 {
74	status = "okay";
75};
76
77&fpd_dma_chan4 {
78	status = "okay";
79	xlnx,include-sg; /* for testing purpose */
80};
81
82&fpd_dma_chan5 {
83	status = "okay";
84};
85
86&fpd_dma_chan6 {
87	status = "okay";
88	xlnx,include-sg; /* for testing purpose */
89};
90
91&fpd_dma_chan7 {
92	status = "okay";
93};
94
95&fpd_dma_chan8 {
96	status = "okay";
97	xlnx,include-sg; /* for testing purpose */
98};
99
100&lpd_dma_chan1 {
101	status = "okay";
102};
103
104&lpd_dma_chan2 {
105	status = "okay";
106};
107
108&lpd_dma_chan3 {
109	status = "okay";
110};
111
112&lpd_dma_chan4 {
113	status = "okay";
114};
115
116&lpd_dma_chan5 {
117	status = "okay";
118};
119
120&lpd_dma_chan6 {
121	status = "okay";
122};
123
124&lpd_dma_chan7 {
125	status = "okay";
126};
127
128&lpd_dma_chan8 {
129	status = "okay";
130};
131
132&xlnx_dp {
133	status = "okay";
134};
135
136&xlnx_dpdma {
137	status = "okay";
138};
139
140&gem0 {
141	status = "okay";
142	local-mac-address = [00 0a 35 00 02 90];
143	phy-mode = "rgmii-id";
144	phy-handle = <&ethernet_phy0>;
145	ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
146		reg = <0>;
147	};
148	ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
149		reg = <7>;
150	};
151	ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
152		reg = <3>;
153	};
154	ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
155		reg = <8>;
156	};
157};
158
159&gem1 {
160	status = "okay";
161	local-mac-address = [00 0a 35 00 02 91];
162	phy-mode = "rgmii-id";
163	phy-handle = <&ethernet_phy7>;
164};
165
166&gem2 {
167	status = "okay";
168	local-mac-address = [00 0a 35 00 02 92];
169	phy-mode = "rgmii-id";
170	phy-handle = <&ethernet_phy3>;
171};
172
173&gem3 {
174	status = "okay";
175	local-mac-address = [00 0a 35 00 02 93];
176	phy-mode = "rgmii-id";
177	phy-handle = <&ethernet_phy8>;
178};
179
180&gpio {
181	status = "okay";
182};
183
184&gpu {
185	status = "okay";
186};
187
188&i2c0 {
189	clock-frequency = <400000>;
190	status = "okay";
191};
192
193&i2c1 {
194	clock-frequency = <400000>;
195	status = "okay";
196};
197
198&rtc {
199	status = "okay";
200};
201
202&uart0 {
203	status = "okay";
204};
205
206&uart1 {
207	status = "okay";
208};
209
210&watchdog0 {
211	status = "okay";
212};
213