1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
4 *
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14
15/ {
16	model = "ZynqMP zc1751-xm015-dc1 RevA";
17	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
18
19	aliases {
20		ethernet0 = &gem3;
21		gpio0 = &gpio;
22		i2c0 = &i2c1;
23		mmc0 = &sdhci0;
24		mmc1 = &sdhci1;
25		rtc0 = &rtc;
26		serial0 = &uart0;
27		spi0 = &qspi;
28		usb0 = &usb0;
29	};
30
31	chosen {
32		bootargs = "earlycon";
33		stdout-path = "serial0:115200n8";
34	};
35
36	memory@0 {
37		device_type = "memory";
38		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
39	};
40};
41
42&fpd_dma_chan1 {
43	status = "okay";
44};
45
46&fpd_dma_chan2 {
47	status = "okay";
48};
49
50&fpd_dma_chan3 {
51	status = "okay";
52};
53
54&fpd_dma_chan4 {
55	status = "okay";
56};
57
58&fpd_dma_chan5 {
59	status = "okay";
60};
61
62&fpd_dma_chan6 {
63	status = "okay";
64};
65
66&fpd_dma_chan7 {
67	status = "okay";
68};
69
70&fpd_dma_chan8 {
71	status = "okay";
72};
73
74&gem3 {
75	status = "okay";
76	phy-handle = <&phy0>;
77	phy-mode = "rgmii-id";
78	phy0: phy@0 {
79		reg = <0>;
80	};
81};
82
83&gpio {
84	status = "okay";
85};
86
87&gpu {
88	status = "okay";
89};
90
91&i2c1 {
92	status = "okay";
93	clock-frequency = <400000>;
94
95	eeprom: eeprom@55 {
96		compatible = "atmel,24c64"; /* 24AA64 */
97		reg = <0x55>;
98	};
99};
100
101&qspi {
102	status = "okay";
103	flash@0 {
104		compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */
105		#address-cells = <1>;
106		#size-cells = <1>;
107		reg = <0x0>;
108		spi-tx-bus-width = <1>;
109		spi-rx-bus-width = <4>;
110		spi-max-frequency = <108000000>; /* Based on DC1 spec */
111		partition@qspi-fsbl-uboot { /* for testing purpose */
112			label = "qspi-fsbl-uboot";
113			reg = <0x0 0x100000>;
114		};
115		partition@qspi-linux { /* for testing purpose */
116			label = "qspi-linux";
117			reg = <0x100000 0x500000>;
118		};
119		partition@qspi-device-tree { /* for testing purpose */
120			label = "qspi-device-tree";
121			reg = <0x600000 0x20000>;
122		};
123		partition@qspi-rootfs { /* for testing purpose */
124			label = "qspi-rootfs";
125			reg = <0x620000 0x5E0000>;
126		};
127	};
128};
129
130&rtc {
131	status = "okay";
132};
133
134&sata {
135	status = "okay";
136	/* SATA phy OOB timing settings */
137	ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
138	ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
139	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
140	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
141	ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
142	ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
143	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
144	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
145};
146
147/* eMMC */
148&sdhci0 {
149	status = "okay";
150	bus-width = <8>;
151	xlnx,mio_bank = <0>;
152};
153
154/* SD1 with level shifter */
155&sdhci1 {
156	status = "okay";
157	no-1-8-v;       /* for 1.0 silicon */
158	xlnx,mio_bank = <1>;
159};
160
161&uart0 {
162	status = "okay";
163};
164
165/* ULPI SMSC USB3320 */
166&usb0 {
167	status = "okay";
168};
169
170&dwc3_0 {
171	status = "okay";
172	dr_mode = "host";
173};
174
175&xilinx_drm {
176	status = "okay";
177};
178
179&xlnx_dp {
180	status = "okay";
181};
182
183&xlnx_dp_sub {
184	status = "okay";
185	xlnx,vid-clk-pl;
186};
187
188&xlnx_dp_snd_pcm0 {
189	status = "okay";
190};
191
192&xlnx_dp_snd_pcm1 {
193	status = "okay";
194};
195
196&xlnx_dp_snd_card {
197	status = "okay";
198};
199
200&xlnx_dp_snd_codec0 {
201	status = "okay";
202};
203
204&xlnx_dpdma {
205	status = "okay";
206};
207